I'm having some issues with the TLV320AIC20K which seem to center on the SMARTDM and autocascade detection.
Following the rising edge of reset-, ACD is expected to do it's thing to create the smartdm addresses for the cascaded devices (I'm using the max of 8 devices).
Post reset, there appears to be "contention" on the common "DOUT" serial bus.
It seems as though one of the devices is not driving it's ADC data out during the correct time slot...and another slot seems to be high Z floating.
Aside from the brief discussion on ACD (page 25 of SLAS363D), is there more detail on the whole SMARTDM and ACD processes?
Once the reset process is done, what actually is triggering each device to dump it's data to the DOUT bus? [MCLK? or BCLK? FS, FSD???]
Are there any logic diagrams for the slot managment circuitry?