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PCM4222: Interfacing multiple chip data outputs to a CoolAudio 1401 ADAT encoder/output

Bret Teegarden
Prodigy 30 points
Part Number: PCM4222

I have designed an 8 channel digital output card using 4 PCM4222 chips, following very close to the PCM4222-EVAL board and schematic. The only difference is in the output stage where I am using a CoolAudio 1401 ADAT Lightpipe encoding chip. I measure accurate clocks all the way through the system and am getting audio through to the PCM chips and can see a data stream coming from the PCM chips and at the CoolAudio 1401 data inputs, but am curious if the operation of the PCM4222 with its clock divided by 2 is creating a mismatch with the CoolAudio 1401 that is operating a full clock speed (MCLK). I was wondering, since I am not using a DIT/AES/SPDIF output like the EVAL board if there some addition step I need to take to get synchronization. The CoolAudio chip does not utilize the BCLK and LRCLK signals (or an I2 buss) and the documentation from TI is not very helpful in using multiple PCM4222 chips in concert with each other. I am not asking for a direct solution but am seeking guidance on where to look for more information as CoolAudio provides no support other than their data sheet. If any one has been down this road before I would appreciate any advice. Plus, I am open to constructing an ADAT output stream via other means than the CoolAudio chip if one is available. Thank you in advance.

  • 0
    TI__Guru 57800 points

    Hi, Bret,

    Welcome to E2E, Thanks for your interest in our products!.

    I think we might need more information about the clock configuration of your system in order to identify if there could be a problem. From CoolAudio 1404 datasheet, it seems that this device only requires a frame clock (WCLK) source to generate all the internal clocks. This clock should be provided from the Digital Audio Master device (That can be one of the PCM4222). Could you please provide more information about the clocking structure of your system?, a block diagram would be useful. Also, I would recommend you to take  a look to the following app note about Digital Audio clocking.

    Audio Serial Interface Configurations for Audio Codecs (SLAA469) .

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0
    Prodigy 30 points

    Thank you Diego, my clock configuration is exactly like the EVAL board, with the CoolAudio 1401 replacing the the DIT. The DIT normally is fed MCLK, BCLK and LRCLK but the CoolAudio only supports a MCLK as you stated. The MCLK to the CoolAudio 1404 is taken before the FlipFlop that divides the MCLK by 2 to feed the PCM4222. My MCLK is generated by a choice of two oscillators (22.xxxMHz and 24.xxxMHz) or an external WCLK input. I used the EVAL board as a basis for this setup. I am examining the document you recommended to see if I can glean any information for a solution. Also, I will try to put together a block diagram and upload. I am questioning if the serial audio data coming from the PCM4222s are the correct sample rate for the CoolAudio 1404 since the MCLK being fed to the 4222s are 1/2 the rate of the main system rate.

  • 0 in reply to Bret Teegarden
    TI__Guru 57800 points

    Hi, Bret,

    Thanks for the Feedback. The sample rate supported by the CoolAudio IC is 48KHz, hence a 48KHz signal should be provided to WDCLK pin. The internal clocks required for the operation of the 1401 are generated by the internal PLL from 48KHz clock. This clock can be generated by a PCM4222 (LRCK) acting as master device.

    The MCLK clock that is required by the PCM4222's should have a frequency of 256 times the base sample rate (44.1KHz or 48KHz), this is accomplished by dividing the oscillators you mention by 2. This requirement is specific for the PCM's, it will not affect the 1401.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 30 points

    Thank you so much Diego. I figured as much on the clock frequencies for the 1401. The PCM4222 documentation is pretty vague on using several chips in a multi-channel implementation that doesn't use an I2 buss. I was wondering how critical the use of BCLK and LRCLK are to the operation of the PCM4222 in a multi-channel system. Right now I have the pins for each of these connected in a buss trace so all 4 PCM4222 have their BCLK and LRCLK pins connected together respectively. I have jumpers to pull the Slave/Master pins LO or HIGH on each PCM4222. I have tried multiple combinations of having the chips in either slave or master mode with no avail. Do these pins really need to be connected to anything? I thought I would ask before I begin severing traces...