TLV320AIC24K: Getting ACD (automatic cascade detection) to work

Hi, Kenn,

Welcome to E2E and thank you for your interest in our products!

We will take a look at this and will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

I'm feeding the CODEC an MCLK from an external oscillator (AVX Corp, KC5032A32.7680CMGE00).  The clock is running at 1.8 Vdc.  The datasheet is unclear about what the clock voltage should be.  I assumed it should match DVDD, which is 1.8 Vdc, but figure 1 on page 14 implies that MCLK should be more than 1.8 Vdc given it shows a threshold of 2.4 Vdc.

What should the MCLK voltage be?  DVDD?  IOVDD?  DRVDD?  AVDD?  I assumed DVDD, but that assumption may be wrong.

Hi, Kenn,

Thank you for provide the MCLK information.

Actually, the digital I/O levels are determined by IOVDD. So, in your case there shouldn't be any issue since the VOH is 0.8xIOVDD and the VOL is 0.1xIOVDD.

Have you verified that the hardware reset is completed? The ACD requires 132MCLKs after reset to complete operation. Then, you need to ensure that the rise time of H/W RESET is less than the MCLK period and that it satisfies setup time requirement of 2ns with respect to MCLK rise-edge.

Best regards,
Luis Fernando Rodríguez S.

I used a D flip-flop (NC7SZ175P6X) to ensure the reset timing is correct.  The "D" input is tied to IOVDD.  The "C" (active low) input is fed the reset signal.  The "Clk" input is fed MCLK.  And finally the "Q" output goes to the Reset (active low) input on all CODECs.  I verified the timing with my TDS scope, and an HP logic analyzer.

I inserted a dual schmitt trigger (NC7WZ14P6X) between the output of my 32.768 MHz oscillator and the MCLK inputs on the CODECs, hoping that more drive might help.  It made no difference.  What is the input capacitance of the MCLK input?  The schmitt trigger I'm using can easily drive a 100 pf load.  I'm currently loading the oscillator with two CODECs and the D flip-flop mentioned above, plus the PCB traces.

I have disconnected the PCM Din (pin 18) signal from the OMAP processor (which is the only PCM input on the CODECs).  I've left the SCLK, FS, and Dout signals (which are all outputs from the CODEC) connected to the OMAP processor.  My reasoning here was to rule out the OMAP processor messing up things.  I guess my next step is to disconnect all four PCM signals and see what happens.

I still get an SCLK of 341.3 kHz and FS of 2.666 kHz.  Are these the default frequencies for these outputs?  It's most certainly not the frequencies that should result for the values I'm specifying for N, M, and P.  I've set P to "0", which maps to "8".  I've set N to "1", and M to "32".  My my reckoning FS should be 8 kHz (32.768 MHz / (16 * 8 * 1 * 32), and for two CODECs running in continuous mode, SCLK should be 512 kHz.  For 4 CODECs running in continuous mode SCLK should be 1.024 MHz.  That's not what I see.

As previously mentioned, I am currently running two CODECs (one master, one slave).  The FS signal is being measured from the master CODEC.  I see no activity on the slave's FS output.  I don't know if this is normal.

I continue to struggle getting ACD to work.  Today was not very productive.

I have now breadboarded two inter-connected TLV320AIC24K CODECs (one master, one slave).  I mounted the CODEC chips on carrier boards.  I currently have no microprocessor connected to the CODEC's PCM serial bus nor the I2C bus, so the CODECs are just coming up in their default configuration with no interference from any external hardware.  I've used a D-flip-flop to enforce reset timing as per figure 1 on page 14 of the data sheet.  My measured times are TwH=12.4 nsec, TwL=10.8 nsec, Th1=6.4 nsec, Tsu1= 26 nsec.  There's a bit of slewing on the 32.768 MHz clock, probably as a consequence of the breadboard capacitance.

The good news is the breadboarded setup is producing exactly the same results as the target platform does:

  With one CODEC: MCLK=32.768 MHz, SCLK=170.7 kHz, FS=2666 Hz

  WIth two CODECs: MCLK=32.768 MHz, SCLK=1.365 MHz, FS=2666 Hz

The bad news is the breadboarded setup is producing exactly the same results as the target platform.  I was hoping by eliminating the microprocessor (no possible hardware interference, no software mucking with CODEC registers), that ACD would work.  It does not appear to, or maybe I'm not looking at things correctly.

Questions:

1) Is the default sample rate for these CODECs 2.666 kHz?  That seems to be the case.  That is a surprisingly low sample rate, with only a 1.2ish kHz audio bandwith.

2) How many timeslots should I expect on the serial PCM bus when there are two CODECs?  When I have one CODEC in "programming" mode, I see 4 time slots.  That makes sense to me.  When I have two CODECs, I'm seeing 32 time slots.  I was expecting to see 8 time slots.  I should only see 32 timeslots with 8 interconnected CODECs, no?

3) FS coming from the slave CODEC is about four time-slots later in time as compared to FS coming from the master CODEC.  This seems reasonable to me.  Is this what you expect?

4) FS pulse coming from the master CODEC is at 1.8 Vdc for logic-high and 0 Vdc for logic-low, but the FS pulse coming from the slave is only at 1.4 Vdc for logic-high (logic-low is 0 Vdc).  That does not seem right.  What's worse, logic-high for Dout (pin 17) is at 1.8 Vdc (good), but logic-low is at 1.2 Vdc.  That does not seem correct.  If I disconnect Dout of the Master from Dout of the slave, then logic-low of the master CODEC is 0 Vdc.  The two CODECs are fighting over what the state of Dout should be.  Note that while there is a reasonable Dout signal coming from the master, the Dout signal on the slave is stuck high.  Your thoughts?  Maybe this is a consequence of ACD not working.

4) For my target board, when I set a bit that is "shared" across CODECs, does it matter which I2C address I write the value to?  I assumed it did not matter, and have been writing to address 0x40.