Part Number: TLV320DAC3100
Hi all,
My customer has faced the problem about the excessive current at SPK out when turning on the system power like cold start.
At the -30-dec C, the excessive current is getting large and the system is shutdown.
At the room temp or +70-deg C, there is some excessive current (not so large) during about 130ms but the system is not shutdown.
When turning the power back on immediately, there is no excessive current .
Is there any solution for resolving this problem?
Currently their development stage is almost final, and they can modify only the register setting.
The speaker impedance is 8-ohm.
The setting value to registers is as follows;
0x00 0x00 // Select Page 0
0x01, 0x01 // RESET
0x04, 0x03 // PLL_clkin = MCLK,codec_clkin = PLL_CLK
0x06, 0x08 // J = 8
0x07, 0x00 // D = 0000, D(13:8) = 0, D(7:0) = 0
0x08, 0x00 // PLL D-Value LSB
0x05, 0x91 // PLL Power up, P = 1, R = 1
0x0b, 0x88 // NDAC is powered up and set to 8
0x0c, 0x82 // MDAC is powered up and set to 2
0x0d, 0x00 // DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
0x0e, 0x80 // DAC DOSR_VAL LSB
0x1b, 0x00 // mode is i2s, wordlength is 16, slave mode
0x74, 0x00 // DAC => volume control thru pin disable
0x00 0x01 // Select Page 1
0x1E, 0x02 // SPK power-up control bits remain unchanged on
// short-circuit detection.
0x1f, 0x04 // (b) Program common-mode voltage (defalut = 1.35 V)
0x21, 0x4e // De-pop, Power on = 1.22s, Step time = 4 ms
0x23, 0x40 // LDAC routed to HPL out, RDAC not routed anywhere
0x28, 0x02 // Unmute HPL, set gain = 0 db
0x29, 0x02 // Unmute HPR, set gain = 0 dB
0x2a, 0x1c // Unmute Class-D, set gain = 24 dB
0x20, 0x86 // Power-up Class-D driver
0x24, 0x00 // Enable HPL output analog volume, set = -9 dB
0x25, 0x00 // Enable HPR output analog volume, set = -9 dB
0x26, 0xFF // Enable Class-D output analog volume, set = ** dB <--
0x00 0x00 // Select Page 0
0x3f, 0x90 // Powerup DAC left channels (soft step enabled)
0x41, 0x00 // DAC Left gain = 0 dB
0x42, 0xd4 // DAC Right gain = -22 dB
0x40, 0x04 // UnMute DAC left and right channels
0x19, 0x00 // CDIV_CLKIN = MCLK (default)
0x1a, 0x81 // CLKOUT divider M = 1, CLKOUT M --> power on
0x33, 0x10 // Set GPIO to CLKOUT
Regards,
Toshi