Hello,
Regarding P0_R4: Clock Setting Register 1, I cannot find much information as to how to use Low PLL Clock Range vs High PLL Clock Range and what it changes in the overall functionality.
Both low and high range windows overlap eachother.... so how do I know what to use if my PLL clock is within both?
The AVdd to the CODEC is 1.8V.
In document SLA5557, page 77, Table 2-26 PLL_CLK Frequency Range:
PLL Mode 0: Min PLL_CLK is 80MHz and Max PLL_CLK is 132MHz.
PLL Mode 1: Min PLL_CLK is 92MHz and Max PLL_CLK is 137MHz.
As for the CODEC, MCLK is 2.4576MHz is coming from a 50% duty PWM out of an MCU.
MCLK pin is input to PLL and PLL pin is CODEC_CLKIN (P0_R4 = 0x03).
PLL configured as follows: R=1, J=4, D=0, P=1, NDAC/NADC = 4, MDAC/MADC=12, AOSR=256.
This equates to CODEC_CLKIN= 98.304MHz and as you can see this is well inside both PLL_CLK frequency range windows.
So what value do I use for P0_R4_B6? High range or low range?
My end-result settings makes ADC_CLK = 24576KHz, ADC_MOD_CLK = 2048KHz, ADC_FS = 8KHz.
Also, in document SLA5557 page 3 at the very end, it says "The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.". Further down on page 77 in section 2.7.1 PLL, it states that PLL_CLKIN/P must be greater than 512KHz but less than 20MHz. So is 50MHz a typo?
Thanks,
Benoit