This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3204: PLL clock range configuration

Part Number: TLV320AIC3204

Hello,

Regarding P0_R4: Clock Setting Register 1, I cannot find much information as to how to use Low PLL Clock Range vs High PLL Clock Range and what it changes in the overall functionality.

Both low and high range windows overlap eachother.... so how do I know what to use if my PLL clock is within both?

The AVdd to the CODEC is 1.8V.

In document SLA5557, page 77, Table 2-26 PLL_CLK Frequency Range:

PLL Mode 0: Min PLL_CLK is 80MHz and Max PLL_CLK is 132MHz.

PLL Mode 1: Min PLL_CLK is 92MHz and Max PLL_CLK is 137MHz.

As for the CODEC, MCLK is 2.4576MHz is coming from a 50% duty PWM out of an MCU.

MCLK pin is input to PLL and PLL pin is CODEC_CLKIN (P0_R4 = 0x03).

PLL configured as follows: R=1, J=4, D=0, P=1, NDAC/NADC = 4, MDAC/MADC=12, AOSR=256.

This equates to CODEC_CLKIN= 98.304MHz and as you can see this is well inside both PLL_CLK frequency range windows.

So what value do I use for P0_R4_B6? High range or low range?

My end-result settings makes ADC_CLK = 24576KHz, ADC_MOD_CLK = 2048KHz, ADC_FS = 8KHz.

Also, in document SLA5557 page 3 at the very end, it says "The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.". Further down on page 77 in section 2.7.1 PLL, it states that PLL_CLKIN/P must be greater than 512KHz but less than 20MHz. So is 50MHz a typo?

Thanks,

Benoit

  • Hi, Benoit,

    If your PLL_CLK respects both PLL Modes ranges, you may configure the PLL in any of these modes. Basically, the difference is the frequencies range that the PLL_CLK can achieve.

    PLL Clock Mode 0 accepts an extended frequency range. However, the PLL Clock Mode 1 accepts a higher maximum PLL_CLK frequency. It is a trade off between range and max frequency. So, if your PLL_CLK is 98.304MHz, you may use any of these modes. There won't be any difference.

    Regarding your comment about SLAA557 page 3, this comment is correct. The difference is that the first comment is related to the input clock range. You may connect an input clock from 512KHz to 50MHz. The second comment refers to the PLL_CLKIN/P value. The result of this division should be between 512KHz and 20MHz. For example, you may have a MCLK = 40MHz and P = 8. The input clock would be in the range 512KHz - 50MHz and PLL_CLKIN/P results in 5MHz (which is in the range 512KHz - 20MHz).

    Best regards,
    Luis Fernando Rodríguez S.
  • Hello Luis,

    Thanks for the reply. Understood for the PLL clock range.

    As for the second part, I guess I am well within specs as the CODEC's MCLK is receiving a 50% duty PWM from an MCU and the frequency is 2.4576MHz.

    I have P0_R4 set as MCLK is input to PLL and PLL is CODEC_CLKIN. Then I have P=1, R=1, J=40, D=0.

    Using AIC032CS, these values show that CODEC_CLKIN = 98.304MHz and MCLK @ 2.4576MHz / P=1 = 2.4576MHz so this is correct (512kHz >= value <= 20MHz).

    As for the NDAC/MDAC/DOSR / NADC/MADC/AOSR values, ultimately I need 8kHz audio. That's what I currently have but I need to make sure that I am not violating any rules.

    What is the difference in using an NADC value higher than MADC compared to an NADC lower than MADC?

    Thanks again,

    Benoit

  • Hi, Benoit,

    Regarding the N and M dividers, it is recommended to use a higher M value as mentioned in SLAA557:

    "To a large degree NADC and MADC can be chosen independently in the range of 1 to 128. In general, NADC should be as large as possible as long as the following condition can still be met:
    MADC * AOSR / 32 ≥ RC"

    RC - Resource class

    This condition is suggested to get the best results with the selected processing block.

    Best regards,
    Luis Fernando Rodríguez S.
  • Ok. I am not sure I fully understand the RC portion either, many of the features of this CODEC are quite above my head quite frankly... I don't know what biquads, FIR, IIR and Decimation filters are either.

    I have set NADC to 32, MADC to 3 and AOSR to 128. This gives a calculation of MADC * AOSR / 32 = 48. This is quite above the highest RC value in Table 5-4 <ADC Processing Blocks>.

    All I want is 8-bit 8kHz audio with an MCLK of 2.4576MHz and a BCLK of 128kHz. That's it. So far so good, all works, but I need to make sure that I do not violate any settings either.

    If you have more suggestions you can provide, then it's always appreciated.

    Otherwise I think I'll be good for now.

    Thanks so much,

    Benoit
  • Hi, Benoit,

    Based on the PLL and dividers values that you provided, all the conditions seem to be in order.

    Please let me know if you have additional questions or comments about this codec.

    Best regards,
    Luis Fernando Rodríguez S.