The DC offset as specification.
Hello,
Regarding to the DC offset on TLV320ADC3101, my customer is asking some question.
I know that this device has some dc offset on input block and this value is not constant each device.
The dither control register (Page 1 / Register 26) is used to reduce offset.
(Question)
(1) Can this offset be characterization as specification?
(Like a generally ADC offset error on data sheet.)
If possible could you please tell me?
(2)Is the mechanism of this offset same as generally ADC offset error?
Or is there the relation of internal common mode voltage in the input block.?
Regards,
Tao2199