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TLV320ADC3101: PPL setting on Fs=24.615KHz

Tao_2199
Genius 5770 points
Part Number: TLV320ADC3101

Hello,

 

Regarding to the PPL setting on TLV320ADC3101, my customer is asking a question.

Maybe I think that this setting is correct but I cannot check it because we don’t have EVM yet.

I am asking the PLL setting just in case.

 

(ADC I2S Output)

Fs=24.615KHz

Data length =16bit

BCLK=787.692KHz

(PLL)

R=1,J=5,D=12,P=1

NADC=13, MADC=2, AOSR=128, N=8

 

(Questions)

(1) I will attached PLL setting. Please refer attached file.

Their setting are correct?

 

(2) I will use ADC Processing Block (PRB_R1/R2: IIR/ BIQUAD) and not use ADC miniDSP.

In that case, they should need to configure the IADC (page 0 / register 21) or not?

Number of instructions of minDSP <- IADC?

Or instruction count of PRB_R1/R2(188/244) <- IADC?

 

Regards,

Tao2199

ADC_PLL_Setting_170314.xlsx

  • 0
    Genius 5770 points

    Hello,

     

    As additional information,

    They have already been checking it on their original target board and it seems that there is no problem.

    But they are not sure whether this setting is correct because output Fs is special.

    I cannot prepare EVM yet.

     

    Regards,

    Tao2199

  • 0 in reply to Tao_2199
    TI__Guru* 84915 points
    Hello, Tao,

    1) The PLL and clock dividers settings are all correct. All the conditions in datasheet are respected. So, there shouldn't be any problem.

    2) Since the miniDSP will not be in use, customer may leave the IADC parameter in default value. There's no need configure it.

    Best regards,
    Luis Fernando Rodríguez S.