Having a lot of trouble getting the PLL to give us a PLL locked status (0x28 bit 4)
We have a 25MHz input clock and even the calculations are problematic because the datasheet seems to have errors in it:
From page 34:
When the PLL is enabled and D /= 0000, the following conditions must be satisfied:
6.667MHz = PLLCLK _IN / P = 20MHz
64MHz < (PLLCK IN x K x R / P) < 100MHz
4 = J = 11
R = 1
clearly J is not limited to either 4 or 11 and R doesn't have to be =1. So I'm assuming that this really means:
4 <= J <= 11
R >= 1
if we look at this example :
MCLK = 12MHz and fSref = 44.1kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
No where in the datasheet can I figure out how N=2048 is actually set. I find lots of references to the fact that the divide value is being used and what the value should be, but nothing that tells which register sets it.
The formula in equation 1
(PLLCKIN R J.D)/P
also appears to be incorrect. The divide values when R and P are set is actually R+1 and P+1
So shouldn't this equation be
(PLLCLKIN (R+1) J.D)/(P+1)
??
The relust of PLLCLKIN/P when P=1 is not PLLCLKIN it's PLLCLKIN/2
