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PCM3070: PCM3070 PLL behave abnormal at 192 kHz Fs

Aleksey Starovoytov
Intellectual 400 points
Part Number: PCM3070

Hello everyone.

We do use PCM3070 as a digital mixer that receives I2S mixes it with analog signal and outputs back to I2S.
We did generated a script for it via PurePath. It is all working great for all of the sampling rates up to 88.1k.
Unfortunately, at 96 and higher Fs it makes a loud noise. By doing debugging I have find out that if we not using PLL we have no noise.
However, I have not found correct register settings to made system work at lower Fs without PLL and give me quality sound.

Here is the settings that we use w/ PLL

( 0x30, 0x05, 0x91); // P=1, R=1
( 0x30, 0x06, 0x04); // J=4
( 0x30, 0x07, 0x00); // D=00 (MSB)
( 0x30, 0x08, 0x00); // D=00 (LSB)
( 0x30, 0x04, 0x13); // PLL_clkin = BCLK, codec_clkin = PLL_CLK
( 0x30, 0x0B, 0x81); // NDAC = 1, divider powered on
( 0x30, 0x0C, 0x88); // MDAC = 8, divider powered on
( 0x30, 0x0D, 0x00); // DOSR = 128 (MSB)
( 0x30, 0x0E, 0x80); // DOSR = 128 (LSB)
( 0x30, 0x12, 0x01); // NADC = 1, divider powered off
( 0x30, 0x13, 0x88); // MADC = 8, divider powered on
( 0x30, 0x14, 0x80); // AOSR = 128

 MCLK = 128*Fs

BCLK = 64*Fs

Any suggestions?

  • 0
    TI__Guru 57800 points

    Hi, Alexey,

    Welcome to E2E, Thanks for your interest in our products!.

    Regarding your question, It seems that register 0x04 is not correctly programmed as it is writing to a reserved value and is configuring MCLK as the PLL_clkin source, the correct value should be 0x07 instead of 0x13. Once this is fixed, you need to make sure that the PLL parameters are compliant with the limits mentioned in page 56 of the PCM3070 Application reference guide.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 400 points
    Thanks Diego.

    That was a good catch. This means that we were using MCLK all of the time.
    However, this is not the main issue. Our issue is that we have variable sampling rate I2S signal that we need to mix analog with.
    When we have it at 44.1k, 48k ecs. up to 88.1k everything works as it should; however, when we get higher rates, especially 192k, looks like we start to overclock the audio codec. So, the question is, is there any possible common register settings for supporting all of the rates with good sound quality.
    Or, is there a way to sense sampling rate change and output interrupt signal when it happens. Also, it would be grate to have a read-back off what rate the codec sees.

    Best Regards

    Aleksey
  • 0 in reply to Aleksey Starovoytov
    TI__Guru 57800 points

    Hi, Aleksey,

    Unfortunately, there is no way to make the device detect and report the sample rate used. The PLL parameters  should be configured properly for each sample rate used in order to get a good audio performance. Some configurations could work with different sample rates properly, but for some cases (like 192K or so) the PLL dividers should be updated to make the parameters compliant with the specs.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer