DAC3100 has internal PLL that could be used to generate internal clocks.
As per datasheet, PLL can be configured to generate clocks from incoming BCLK,
There are many dividers (up to DAC_fs). DAC_fs can be acheived with lots of divider combinations. Is there a rule to set CODEC_CLKIN, DAC_CLK, DAC_MOD_CLK, relative to DAC_fs?
I would like to know the best way (proper values) for dividers (R, P, J, D, DOSR, NDAC, MDAC) to acheive, for example, 11025 (BCLK = 352800, I2S).
I am not able to get good audio with (R=J=8, D=0, P=1, NDAC=2, MDAC=8, DOSR=128).
Thanks.
