TLV320AIC3204: PLL Configuration Parameter Document Typo???

Table 2-27 ("PLL Example Configurations") of the TLV320AIC3204 Application Reference Guide shows PLL parameters for various MCLK input frequencies to generate 44.1KHz and 48KHz sampling rates.

For MCLK=12MHz, the table entry math for 48KHz sampling seems correct: (12MHz * 7.168) / (2 * 7 * 128) = 48KHz

However, the table entry math for 44.1KHz yields: (12MHz * 7.560) / (3 * 5 * 128) = 47.250KHz

I believe the PLLD parameter should be 056 instead of 560, yielding: (12MHz * 7.056) / (3 * 5 * 128) = 44.1KHz