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TAS2521: Problem with register configurations

Part Number: TAS2521

Hi,

I'm using TAS2521 for audio output.

[Voltages]    - 3.3V with internal LDO enabled. LDO_SEL (pin 8) is High   
[Input I2S]    - 13(data), 14(word clk), 15(bit clk), 16(master clk).
[other pins]    - 19(I2C scl), 20(I2C sda).

SPKVDD and IOVDD are connected to 3.3V

DVDD is connected externally to AVDD


I have another board with I2s master configured at 44100Hz mono output.

I have verified that I2C interface communication is working fine

I am using an 8 ohm speaker.

I have configured TAS2521 with the below values for speaker

# Playback Class-D
# Page switch to Page 0
W 30 00 00
# Assert Software reset
W 30 01 01
# Page Switch to Page 1  
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up.
W 30 02 00
# Page switch to Page 0
W 30 00 00
# Dac Instruction programming PRB #1  
W 30 3c 01
# CODEC_CLKIN=MCLK.MCLK should be 12.288MHz
W 30 04 00
# Codec Interface control Word length = 16bits.BCLK&WCLK inputs.I2S mode.
W 30 1b 00
# Data slot offset 00
W 30 1c 00
# DAC NDAC Powered up, NDAC=1
W 30 0b 81
# DAC MDAC Powered up, MDAC=2
W 30 0c 82
# DAC OSR(9:0)-> DOSR=128
W 30 0d 00
# DAC OSR(9:0)-> DOSR=128
W 30 0e 80
# Only LDAC powered up.Dac path setup LDAC data Mono of LDAC and RDAC. RDAC data disabled.Soft step 1 per Fs.
W 30 3f B0
# DAC volume for Left channel not muted.Right DAC muted.
W 30 40 04
# LDAC digital gain 0dB
W 30 41 00
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on
W 30 01 10
# Output common mode for DAC set to 0.9V (default)
W 30 0a 00
# LDAC AFIR is 6th order FIR filter and Powered up.
W 30 03 00
# SPKL attn. Gain =0dB
W 30 2E 00  
# SPKL driver PGA Gain=6.0dB  
W 30 30 10
# SPK OSCP enabled , OCP Degltich=4, OTP enabled , OTP Deglitch=5
W 30 52 00
# SPK powered up
W 30 2D 02

And I have configured TAS2521 with the below values for headphones

# Playback HP
# Page switch to Page 0
W 30 00 00
# Assert Software reset
W 30 01 01
# Page Switch to Page 1  
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up.
W 30 02 00
# Page switch to Page 0
W 30 00 00
# Dac Instruction programming PRB #1 for Mono routing.
W 30 3C 01
# CODEC_CLKIN=MCLK.MCLK should be 12.288MHz
W 30 04 00
# Codec Interface control Word length = 16bits.BCLK&WCLK inputs.I2S mode.
W 30 1b 00
# Data slot offset 00
W 30 1c 00
# DAC NDAC Powered up, NDAC=1
W 30 0b 81
# DAC MDAC Powered up, MDAC=2
W 30 0c 82
# DAC OSR(9:0)-> DOSR=128
W 30 0d 00
# DAC OSR(9:0)-> DOSR=128
W 30 0e 80
# Only LDAC powered up.Dac path setup LDAC data Mono of LDAC and RDAC. RDAC data disabled.Soft step 1 per Fs.
W 30 3f B0
# DAC volume for Left channel not muted.Right DAC muted.
W 30 40 04
# LDAC digital gain 0dB
W 30 41 00
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on
W 30 01 10
# Output common mode for DAC set to 0.9V (default)
W 30 0a 00
# LDAC AFIR is 6th order FIR filter and Powered up.
W 30 03 00
# Power up HPL
w 30 09 20
#Signal to HPL
w 30 0c 04
# unmute HPL
w 30 10 00

Neither speaker nor headphones are giving any audio output.

Am I missing anything? Please suggest me with a solution.

Thank you.

  • Hi Chandan,

    A colleague of mine will be reviewing your issue soon and will come back to you with further information.

    Best Regards
    José Luis Figueroa
    Audio Applications Engineer
  • Hi Chandan,

    I see this is the same issue as your last post.
    I have verified both register settings on an EVM board and they are fine. Both configurations operate properly on my EVM board.
    There isn't any signal at all on the outputs when you try it?
    Is there a chance you could provide a capture of the I2S signal coming into the device.

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators