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TLV320AIC3254: TLV320IC3254

Part Number: TLV320AIC3254

Application: Microphone (line-in from MIC-pre-amp) CODEC.

Using SPI interface.

 

The code was developed on both a –K and –U EVB.  Both are USB-I2C (and the –K has a switch for SPI.) We have successfully run a 500 Hz tone generator (testing) and our more complex app.

We have accomplished the following:

1.       Now on our target board which goes to production next month.

2.       Have proven our power-supplies (not using internal LDO): 3.3 and 1.8V.

3.       SPI: Chip-select, clock, data.  (We do not have read-back capability on this board, although we did successful read-bask on the K-EVM). SPI clock is 250 kHz (below the 400 limit)

4.       MCLK: Input clock is 3.3V CMOS-19.200 MHz.  (Not used on eval boards).

5.       Since we have ‘accidently’ (see below) have gotten that CODEC running on two different processors (Silicon Labs, and our board processor is a PIC24), we are confident the SPI integrity and our registers addressing is being done correctly.

 

The simple 500 Hz tone generator is loaded.  Nothing happened.  I probed pin 1 (MCLK) and accidently bumped to pin2-BCLK.  It began to run.  I was able to repeat that several times.  However, if pin-1&2 were connected at power-up, nothing.

 

Schematics and Code being furnished by Phil Meyer

 

I suspect it has something to do with using the internal PLL, since the -U and –K eval boards used a 4 MHz clk from the TI USB-IC.

  • Hi, Don,

    Welcome to E2E and thank you for your interest in our products.

    Is MCLK the only clock that you are using? Do you have additional clock signals at BCLK and WCLK?

    BCLK and WCLK are required by the codec in order to start working. If these pins are configured as outputs (master mode, see page 0 / register 27, 29 and 30 to enable this mode), the codec will generate these clocks and it should start working.

    However, if these pins are configured as inputs (slave mode, default configuration), the codec needs of few pulses at BCLK to work. This could explain the accident that you mentioned.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hello Luis, Thank you for your prompt response. MCLK is the only clock source (19.200 MHz). BCLK and WCLK are unconnected.
    FYI I provided the C-Code and schematic to Phil Meyer so you can review. Rich, who programmed this device using GDE and then converting to SPI & C code is now unavailable for several days as he relocates. Alek, my PIC24 programmer, who implemented Rich's code onto the target PIC24 is available and can make register changes. However he is unfamiliar with this IC. Could you suggest the register values to change and we would be happy to try. Thank you, Don
  • Hi, Don,

    Could you provide some additional information, please?

    What sampling rate will be used? How many bits will be transferred per channel? What is the expected frequencies at BCLK and WCLK?

    I can suggest some values once I get this information.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis, I spoke with Rich who set this up, but has no access to his computer (moving).
    1. Sampling rate: 16 kHz
    2. Bits/channel: He is not sure, but was using the EVM-K eval (GDE GUI). Is it in the .cfg file I sent to Phil?
    3. He set up MCLK (19.2 MHz) to be the sole input and the PLL accordingly; assuming the MCLK would be distributed for BCLK. But this was his first time trying this with the C-code and SPI (EVM-K works off of 4 MHz USB). So when we both (at different sites) got it running by touching MCLK briefly to MCLK, the 500 Hz tone appeared.
    4. He was not trying to use WCLK.

    Is this enough info for you? Best Regards, Don
  • Hi, Don,

    I would recommend to add the following register configuration. It configures the PLL and clock dividers correctly based on the information that you provided:

    w 30 00 01
    w 30 02 00
    w 30 00 00
    w 30 04 03
    w 30 05 91
    w 30 06 04
    w 30 07 12 c0
    w 30 0b 87 82
    w 30 12 87 82
    w 30 1b 0c
    w 30 1d 07
    w 30 1e 86

    The code lines are in hex format: w (write) 30 (I2C address) xx (register address) yy (register data) zz (next register data).

    The BCLK and WCLK are configured as outputs. PLL and dividers are configured as below:

    P = R = 1
    J = 4
    D = 4800
    M = 2
    N = 7
    OSR = 128

    Best regards,
    Luis Fernando Rodríguez S.
  • Luis, my programmer will implement today and we have a test scheduled for early AM on 5/3. Will advise results. Thank you for your prompt analysis and response. Don
  • Morning Luis, a question from my programmer, Alek:
    ......
    I have finally had time to look at Luis suggestions and modified the codec init function.

    I added Luis's code at the end of Rich's (500 Hz generator)
    However could you clarify his suggestions?
    How to interpret the this line?
    w 30 07 12 c0
    Is this equivalent to
    w 30 07 12
    w 30 08 c0

    The codec only accepts instructions in pairs of bytes (address, data)..
    ......Thanks , Don
  • Hi, Don,

    Sorry for this confusion. Effectively, the line w 30 07 12 c0 is the equivalent to w 30 07 12 and w 30 08 c0.

    Please let me know if you require additional information.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hello Luis, Problem Solved! Thank you for all of your support. We were able to problem the CODEC using SPI, 19.2 MHZ MCLK (with BCLK and WCLK set as outputs). We can now move on from our test-app to the actual implementation. My DSP programmer has 20 years experince and really likes the GUI development environment. Best Regards, Don