TLV320ADC3001: Non-constant host DSP clock

We are considering using the TLV320ADC3001 in an application in DSP mode. We know that the host processor cannot generate a constant bit clock as it stops the clock between reads and while rotating buffers. It will be able to maintain the approximate data rate, but what will the TLV320ADC3001 do with a non-constant bit clock? Is there an output buffer that can absorb some jitter? What happens when those buffers overrun or underrun? Or does it need a constant bit clock that is constant and the perfect multiple of the system clock in order to not have problems?