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TLV320AIC3268: Question of the TLV320AIC3268 Programming as an I2S to Right Justified Converter

Part Number: TLV320AIC3268
Other Parts Discussed in Thread: SRC4192,

Hi Sirs,

I am programming the AIC3268 as an I2S to Right Justified format converter for my customer. The input and output formats are:

MCLK = 24.576MHz

1. ASI1 (Input, Slave mode) -> BCLK = 1.512MHz, LRCK = 48kHz, 16bit I2S
2. ASI2 (Output, Master mode) -> BCLK = 1.512MHz, LRCK = 48kHz, 16bit RAJ

I am trying to configure the AIC3268 with the following configurations, however, I can get valid BCLK and LRCK output on ASI2, not the Audio Precision culd not decode te data. Would you pls advise if there is missing or mistake with my CodecControl configuration?

PPS configuration:


CC configuration:




  

Thank you and Best regards,

Wayne Chen
05/18/2017


  • Hi, Wayne,

    I would recommend to check several things:

    - Ensure that all the jumpers and switches of the TLV320AIC3268EVM-U are placed in default state.
    - Then, the PurePath Studio configuration seems to be correct. However, I noticed that your PLL configuration is wrong. The PLL_CLK is 196.608MHz, which is too high. I recommend to change the PLL P value from '1' to '2'. Then, modify the MDAC and MADC clocks from '8' to '4'.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hello Luis,

    Thank you for your suggestion. The AP still cannot stable decoding the AIC3268 ASI2's data output, I found the LRCK's high jitter output should be the problem. Would you pls provide suggestion:

    1. Is there is something missing with my ASI1 and ASI2's configurations?
    2. Can we use AIC3268 (software slution) or SRC4192 (hardware solution) to achieve 1.536MHz BCLK, 48kHz, 16bit I2S input, 3.072MHz BCLK, 48kHz, 24bit I2S output with 24.576MHz MCLK?

    Thank you and Best regards,

    Wayne Chen
    05/23/2017
  • Hi Luis,

    Addition to my previous post. My AP can decode stable RJ outout but with 15kHz and 17kHz harmonics I don't know where are they come from.
    Would you please assit me to review if there is missing or mistake? How can I remove those 15kHz and 17kHz components?

    Please refer to my AP, CC and PPS configuration:

    AP Output to ASI1:



    AP Input from ASI2:



    AP Decoded data::


    FFT Plot:


    Decoded RJ waveform:


    Frequency Response:



    CC Interface Setup:


    CC CLK Setup:


    CC I/O Setup:


    PPS MiniDSP Programming:


    I can reduce THD+N by applying 12kHz lowpass filter at AP's input, hwever, it is not acceptable by customer due to its poor frequency response:


    Thank you and Best regards,

    Wayne Chen
    05/23/2017

  • Hi, Wayne Chen

        Recently i am learning how to use the TLV320AIC3268 chip, and i happened to find that you are exploring this chip.

    I found you have many tools to cooperate with your develop, such as you mentioned the tools called AP, CC and PPS. I know PPS means the PurePath Studio, but what about AP and CC ?

    I am wondering whether you can share these tools with me ? I will appreciate it very much!

  • Hi, Wayne,

    All the settings seem to be correct. So, if the audio codec doesn't work properly, you would require of an external SRC such the SRC4192. It supports the data formats that you mentioned and you will not require the TLV320AIC3268 to make this conversion.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi, Tonytao,

    Welcome to E2E and thank you for your interest in our products.

    All the tools that Wayne mentioned can be found on the TLV320AIC3268 product folder:

    www.ti.com/.../toolssoftware
    www.ti.com/.../aicpurepath_studio

    The AP is a laboratory audio precision equipment. This tool is not distributed by Texas Instruments.

    Best regards,
    Luis Fernando Rodríguez S.