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TLV320AIC3254: TLV320AIC3254

Don Moore
Prodigy 170 points
Part Number: TLV320AIC3254

ADC or DAC overload-clipped output

Application: Mono, single-ended input on IN1_L.  Frequency Range: 500-3600 Hz.The nominal desired input level is approximately 0.325 Vrms. The desired output level approx. 0.200 Vrms (fixed gain).  This implementation is voice band input with user defined filter coefficients (DSP) for LOR and LOL outputs (There is one set of coef for LOL and a separate set for LOR). 

The application was successfully developed using both the -K and -U EVMs (but with clipping noted below).  It has now been ported to a micro-processor (using SPI) to configure the CODEC.  The applications works identically on the eval boards and our target.

 The application works to a input level of only 25 mVrms.  Above that level: the device is overloaded and the output waveform is noise. We are providing external 3.3 and 1.8V inputs (internal LDO disabled).

There should be no power consumption (powertune) that limit performance.

Please advise your thoughts on what we have missed. Thank you.

C-Code being sent separately.

  • 0
    TI__Guru* 84915 points
    Hi, Don,

    Could you provide the TLV320AIC3254 schematic portion and the registers configuration, please? This would be very helpful to have a better approach to this issue. Additionally, could you provide the I2S clocks frequencies that you are using?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Guru* 84915 points
    Hi, Don,

    I reviewed the registers configuration and it seems that the AVDD LDO is powered up. I noticed that you mentioned that you are using external power supplies, but bit D0 of LDO Control Register seems to be enabled (page 1 / register 2).

    Additionally, could you try modifying the DOSR value? Could you use 128 for this value and configure the rest of clock dividers as the MADC and NADC?

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 170 points
    I'll ask Phil to send you the schematic. Our clock is 19.2 MHZ (same as with our earlier test case). Using SPI (rather than I2C) running at 250 kHz.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 170 points
    Hi Luis, I'll ask my programmer to make the changes noted. However, I don't understand what you want us to try regarding MADC and NADC.
    Our sampling rate is 16 kHz. 19.2 MHZ MCLK. BCLK and WCLK are configured as outputs and I'm seeing 16 and 384 kHz on those pins. Thanks, Don
  • 0 in reply to Don Moore
    TI__Guru* 84915 points
    Hi, Don,

    I apologize for the confusion.

    I mean, could try configuring DOSR = AOSR = 128, NADC = NDAC = 2, MADC = MDAC = 24? Is it possible in your application? We normally recommend to have AOSR and DOSR configured as 64 or 128.

    Additionally, could you try with different processing blocks? Do you have the same results?

    I didn't find anything to modify in the schematic. However, we suggest to route the unused analog inputs to a 0.47uF capacitor to GND. This will improve the audio codec performance.

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 170 points
    Hi Luis, We used the above settings and the App is running with much higher performance (viewing the modulated RF waveform that uses these 2 baseband signals).

    With just approx. 50 mV (Vin) applied to input of the CODEC, there is 350 mV output (Vout) which is our target. This is too much gain. We want up to 350 mV Vin for same 350 mV Vout. IE overall gain approx =1).

    My programmer who developed this app is not available. Could you take a look and suggest what we can do to stay linear with the higher Vin?

    Best Regards, Don
  • 0 in reply to Don Moore
    TI__Guru* 84915 points
    Hi, Don,

    Is it possible to provide your last registers configuration?

    I would recommend to reduce the analog input gain with page 0 / registers 83-84 and page 1 / registers 59-60. These registers control the ADC gain.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 170 points
    Luis, the latest code is being forwarded to you now.
    1. I misstated my Vin-Vout (CODEC) in prior message Desired CODEC input ( mic-preamp ouput) : 0.325 Vrms. Desired CODEC output (fixed gain): 0.125 Vrms (350 mV-p-p).

    2. Still confused on internal LDO. Pin 31 is pulled down and AVDD (1.8V) is supplied. However, the CODEC did not work until we restored the setting shown in the code. Is this correct?

    Thanks, Don
  • 0 in reply to Don Moore
    Prodigy 170 points
    Luis, I misstated the CODEC I/O again.
    Vin: 0.440 mVrms.
    Vout: 0.175 mVrms
    Don
  • 0 in reply to Don Moore
    TI__Guru* 84915 points
    Hi, Don,

    1.- For these values I would recommend to modify the page 0 / registers 83-84 in order to get the correct gain. You would require a gain around -8dB. So, I suggest to replace the line reg[0][83] = 104 with reg[0][83] = 110. Additionally, could you try disabling the AGC? It is configured with page 0 / register 86.

    2.- You are right. If Pin 31 is pulled down, the codec will be placed in reset mode. So, all registers will be in default state. In order to use the audio codec, you would need to re-configure the registers. However, there's no need to connect an external AVDD power supply. When internal LDO is used, the AVDD voltage is generated internally.

    Best regards,
    Luis Fernando Rodríguez S.