TLV320AIC3254: Data from Codec is not right

Hi,

Welcome to E2E and thank you for your interest in our products!

This definitely is a sampling rate problem. Could you provide the PLL coefficients (P, R, J, D) and the clock dividers (NADC, NDAC, MADC, MDAC, AOSR, DOSR) that you are using? Additionally, could you provide all the clocks frequencies (MCLK, BCLK, WCLK) that you are using?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Thank you very much for the immediate response.
I am using the same project from Ti CSL_I2S_AudioCodec_DMA . I have not changed any of the below settings. They are default settings.
I am new to this CODEC settings. I am sorry if I have not shared all the information you wanted in the below message.
Please let me know if you need any more information to validate my settings.

PLL coefficients and BCLK, WCLK
result = AIC3254_Write( 27, 0x00, hi2c ); // BCLK and WCLK is set as i/p to AIC3204(Slave)
result = AIC3254_Write( 4, 0x07, hi2c ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK
result = AIC3254_Write( 6, 0x08, hi2c ); // PLL setting: J = 32
result = AIC3254_Write( 7, 0, hi2c ); // PLL setting: HI_BYTE(D)
result = AIC3254_Write( 8, 0, hi2c ); // PLL setting: LO_BYTE(D)

(NADC, NDAC, MADC, MDAC, AOSR, DOSR)
result = AIC3254_Write( 5, 0x92, hi2c ); // PLL setting: Power up PLL, P=1 and R=2
result = AIC3254_Write( 13, 0x00, hi2c ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
result = AIC3254_Write( 14, 0x80, hi2c ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
result = AIC3254_Write( 20, 0x80, hi2c ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
result = AIC3254_Write( 11, 0x88, hi2c ); // Power up NDAC and set NDAC value to 4
result = AIC3254_Write( 12, 0x82, hi2c ); // Power up MDAC and set MDAC value to 2
result = AIC3254_Write( 18, 0x88, hi2c ); // Power up NADC and set NADC value to 4
result = AIC3254_Write( 19, 0x82, hi2c ); // Power up MADC and set MADC value to 2
result = AIC3254_Write( 0, 0x01, hi2c ); // Select page 1

Hi,

Could you also provide the BCLK and WCLK values, please? It seems that the BCLK frequency is used as CODEC clock input in this case.

Best regards,
Luis Fernando Rodríguez S.

I can't get the values for BCLK and WCLK values. It is not set in either CODEC or in C5535.I can’t see any other option for the BCLK and WCLK master.

Do you have any example setting these values for 48Khz settings if CODEC sets these pin as an input.

Hi,

Please take a look at the script below. It contains the high-performance configuration with 48KHz settings and BCLK and WCLK as inputs.

###############################################
# High Performance Stereo Playback
###############################################

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.2880 MHz,
# BLCK = 3.072 MHz, WCLK = 48 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NDAC = 1, MDAC = 2
w 30 0b 81 82
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Set the DAC Mode to PRB_P8
w 30 3c 08
#
###############################################

###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input powerup time to 3.1ms (for ADC)
# w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################

###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Unmute LOL/LOR driver, 0dB Gain
w 30 12 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

Best regards,
Luis Fernando Rodríguez S.

Current settings: CODEC is set as i/p for BCLK and WCLK.
I tried setting this as MASTER but everything stopped working.
result = AIC3254_Write( 27, 0x00, hi2c ); // BCLK and WCLK is set as i/p to AIC3204(Slave) changed to
result = AIC3254_Write( 27, 0x0C, hi2c ); // BCLK and WCLK is set as o/p to AIC3204(Master)

This config states # Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.2880 MHz,
# BLCK = 3.072 MHz, WCLK = 48 kHz

From where it is getting BLCK and WCLK? Where to set these settings?
Any details will be helpfull.

Hi,

When WCLK and BCLK are configured as outputs, it is required additional configuration. WCLK is directly configured as the sampling rate. So, there's no additional configuration for WCLK.

However, BCLK pin requires of additional settings:
- Page 0 / Register 29. It is used to configure the BCLK source. It may be DAC_CLK, DAC_MOD_CLK, ADC_CLK or ADC_MOD_CLK. See bits D1-D0 for details.
- Page 0 / Register 30. It is used to enable the BCLK output. The BCLK source is taken and divided by the BCLK N divider.

Best regards,
Luis Fernando Rodríguez S.

Thank you for the update.

1. I made the changes as suggested. After the changes, playback stopped working.   I am now suspecting how it was working before making these changes. 

2. Earlier it was configured as input mode. I2S is configured as slave mode. In this case, how it is getting clocks to stream the data from CODEC. In this case, BCLK/WCLK is set as input so these clocks are not sent to I2S. But I2S gets the data at fs rate. Not sure what rate it is and playback is fine. Basic question comes to my mind is from where I2S is getting the clock to stream the data.

Any idea on how it is working in current settings without setting these BCLK/WCLK. I am now checking if any signals available on the line, I am sure there will be signals on BCLK/WCLK pin on I2S but from where it is coming, is it coming from CODEC (In this case, it is not possible as they are configured as input). It cannot generate by itself in I2S because I2S is configured as SLAVE.  Confused now. Any hints will be very valuable to debug this issue further.

Hi,

Do you have any schematic about this application? As you mentioned, in slave mode, the audio codec is not capable to generate the I2S clocks. So, you would need to verify if the devices connected to the I2S lines are generating the I2S stream.

Best regards,
Luis Fernando Rodríguez S.

The application is CSL_I2S_AudioCodec_DMA project. It is one of the default application from CSL package.

Hardware: eZdsp5535

Tech Ref Manual of eZdsp5535: http://support.spectrumdigital.com/boards/ezdsp5535/revc/files/ezdsp5535_TechRef_RevC.pdf

By default:

Codec file   codec_aic3254.c , BCLK, and WCLK are set as input mode.

AudioCodec_DMA.c (Test code to verify the CSL I2S functionality) , I2S is set as SLAVE. Please see that these are all the default settings from Ti examples only. I have not changed or updated anything.

When this application is run by default, I can hear the clear playback. For ex: I am playing music from PC through eZdsp5535.

There is definitely a valid stream on playback and it is passing through I2S and not sure who is generating the clock or setting the rate.

Hi,

Based on the schematic, the C5535 seems to be the device that is generating the I2S clocks. The clocks are generated on pins P5 and N10. So, if the audio codec is configured in master mode, there could be a collision on the I2S lines. It seems that this application only can be used with the AIC3204 in slave mode.

Best regards,
Luis Fernando Rodríguez S.