How to interface an I2S audio converter to an MSP430

Hi there,

I am working on a design using a MSP430F5438 to analyse an audio stream from a AIC3254. In my case the CODEC is in master mode and generates all clock signal in the Left Justified Mode. I configured the MSP430 in 4-wire SPI mode. With STE (Slave Transmit/receive Enable) connected to the WCLK the interface only receives one channel. If you need both channels then you could take a second SPI interface connected to the same bus but with an inverted STE signal.So no for external components at all.

As mentionned in 'slaa449a.pdf' there is one slight problem that the stream is 16bit and SPI only supports 8bit. In my case I am filling up a larger buffer through DMA. If you fill the buffer from the beginning you will notice that you can't read them as signed integer (16bit) straight away.  MSB(byte) and LSB(byte) are inverted (little endian/big endian). If you start filling the buffer from the end this issue is solved as well.

Good luck

jaiv

Hello-

We are going to be doing the same thing, using the CODEC as a timing master. Could you please send me a little more details on how your code and hookup works? We cannot use any external hardware, and we're using the MSP430F5528 device.

MANY thanks in advance!

Howard

Howard -

Jaiv’s idea is clever! Without any external hardware (i.e., an inverter), you should connect the Codec’s I2S bus to the MSP430’s SPI bus using 3 wire SPI mode. Use one of the DMA channels to transfer the ADC samples into memory. By setting the DMADSTINCR field of DMAxCTL to 10b (“destination address is decremented”) and starting at the end (highest address) of the memory block, you will solve the “Endianness” problem. In other words, the DMAxDA (destination address) should initially point to the end of the buffer. However, the data from the Left and Right channels will be interlaced. The DMAxSZ register should be set to the size of the raw data buffer in bytes, and DMA interrupts enabled, so that you can tell when the raw data buffer is full. Then you can ‘de-interlace’ the data into separate buffers for the left and right channels in software.

Mike

Hi Mike. My programmer is having a heck of a time getting this working. Here is a brief description.

Our audio stream is a 32bit left justified stream, with 16 bits per channel. The stream originates in a CODEC, running as a timing master.

The data output is connected to MSP430F5529 device UCA1_SIMO.

The bit clock is connected to UCA1_SCLK.

The frame sync signal is connected to an input, P4.6. FS rate is 11025 s/s.

We need to write the stream to a ping-pong buffer pair (for subsequent writing to a sd card as an audio wav file), and have three main issues:

1. If we write to the top of the buffer to "solve" the endian issue, the whole buffer has to be re-written to another buffer to be able to output the data correctly ordered to another  device.

2. We cannot get the dma to start consistently in sync with the FS signal.

3. When writing to the sd card (using spi) the interrupts for the entire system appear to be shut down during the writing, causing many problems.

Has anyone else written code that writes an I2S audio stream to a spi connected sd card? If so, your assistance would be appreciated.

Would it be possible to get some assistance directly to my programmer? His name is Layne Phillips, and his email address is LNPSWEng@aol.com. Please cc me on any email traffic so I can be in the loop.

Many thanks, Howard

Hi, I am designing an application to capture the I2S output of an audio codec (TLV320AIC3256) with an MSP430.

Since only the direction from the codec to the MSP is needed, I want to use the codec as the timing master as jaiv suggested and use the WCLK as the MSP's slave select input. Only one channel can be captured this way but this is not a serious drawback for my application.

I would be grateful to hear from jaiv or anyone else who have tried this about any problems or other issues that I may have.

In case I need both channels, is it possible to use the WCLK to initialise the SPI transfer, thus avoiding the syncronisation problem that Howard mentioned, and then "latch" the SPI in "selected" mode so that the MSP keeps receiving words indefinetely using DMA? Maybe turn the WCLK off from the codec side after the reception starts so that the STE remains low?

I have seen that the codec's outpout word length is configurable to 16, 20, 24 or 32 bits. Does this mean that the resolution of each value is increased accordingly, or that for 32-bit word length two 16-bit values are send along with 32 dummy bits? I suspect that the former is the case, however the latter would be preferred  for my case if the left and right values are sent in the first 32 bit clock cycles, when the WCLK is constantly LOW or HI (depending on polarity) so that they can be received as a single SPI frame.

Any info is appreciated,

Thank you in advance,

Giannis

I am still working on the interface between the TLV320AIC3256 and the MSP430 and have stumbled upon the following: The audio codec outputs I2S samples of 64bits, 32bits per channel. Using the TLV320AIC3256 eval board and configuring the word length to 16 bits per channel, the length of each sample is still 64 bits, which makes interfacing with the MSP430 more difficult. Is it possible to configure the codec to output 16bit per channel, left-justified I2S?