Other Parts Discussed in Thread: AM5728, TLV320ADC3101
I'm trying to program DIX4192-Q1 by means of Linux userspace application via SPI protocol. Audio data is sourced to this decoder, passing through following elements:
Microphone -> TLV320ADC3101 -> DIX4192-Q1(data stream encodes into SPDIF) -> DIX4192-Q1(data stream decodes from SPDIF) -> Sitara am5728 processor.
Audio flow is sampled with LRCLK=48000 Hz and BCLK=3.072MHz. Reference clock is sourced from RXCKI = 24.576MHz.
I'm programming it in the next sequence (where "w" means write, and next two numbers are reg addr and new reg value respectively in the hex numeric format ):
/* Reset and power down all modules */
w 0x7f 0x00
w 0x01 0x80
w 0x01 0x00
/* DIR configure */
w 0x0d 0x00
w 0x0e 0x05
/* Set up port A */
w 0x03 0x69
w 0x04 0x0b
/* Set up PLL1*/
w 0x0f 0x22
w 0x10 0x00
w 0x11 0x00
/* Unmute port A and power on all modules, except Port B and DIT */
w 0x03 0x29
w 0x01 0x32
After programming I can see correct LRCLK and BCLK, outputs from DIX on oscilloscope. But there is no any data, outputs from it.
But when I'm firstly programming it with bypassing PLL2 dividers(writing 0x01 value to the 0x0e register), then data flow outputs and clocks are incorrect. And then after changing divider value on what I need, I get expecting result with correct data and clocks on DIX outputs.
It's very strange and uncomfortable way to programming it via Linux userspace app, because in this case, I need to program DIX with bypassing dividers, then send data flow via arecord, write needed divider and abort aplay every time, when I want to start recording.
What am I supposed to do to avoid this steps and get correctly working system after single programming sequence.
