Part Number: TLV320ADC3101
Hello
Would you please adivse your opinion about TLV320ADC3101 clock setting?
<Back Ground>
Customer had chosen TLV320ADC3101 .
In the data sheet p24, we can select ADC_CLKIN for MCLK also BCLK.
Customer use MCLK is chosen , and 2.048MHz,so, ADC_CLKIN=2.048MHz.
But I think customer should use PLL if they use mini_DSP.(Q1)
I am not confident with AOSR value in case fs=8KHz.
Q1 ADC_CLKIN
I guess ADC_CLKIN used in mini_DSP_A, so, if customer use mini_DSP,
customer had better use ADC_CLKIN as large(50MHz) as possible.
( 1024 cycle x 48KHz= 49MHz..)
Therefore, if ADC_CLKIN=2.048MHz and ADC_fs=48KHz, ADC_CLKIN / ADC_fs is only 256 ( cycles).
Customer should use PLL if they use mini_DSP.
... Is this correct?
Q2 AOSR
In case input LRCK(ADC_fs) is 8KHz, what AOSR value is recommended?
To set ASOR=128 is no problem or 256 is recommended?
Customer is concernd about the criteria below.(ASOR=8bit)
2.8 MHz < AOSR × ADC_fs < 6.2 MHz ( eq(6) p79)
Best Regards
