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TAS2505: What's the appropriate register setting for clock output?

Christina Lim
Expert 6345 points
Part Number: TAS2505


Hi,

I'm trying to get 16kHz Fs clock based on a BCLK of 512kHz (resolution : 16 bit). Using the register settings below, I cannot get any output, can you advise the appropriate register required?

Refer to “TAS2505 Application Reference Guide_slau472.pdf”:

4.0.7 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker

Outputs

 

//new settings for TAS2505, 2017.6.19

void CodecInit(unsigned char ucInputLine, unsigned char ucOutputLine)

{

 

    /*       Initialization        */

    CodecReset();

 

    /*       Digital Configuration

     *                       -> PLL_CLK = (PLL_CLKIN x R x J.D)/P

     *                                      -> CODEC_CLKIN = PLL_CLK

     *                                                     -> DAC_Fs = CODEC_CLK_IN / (NDAC.MDAC.DOSR)

     *                                                     -> ADC_Fs = CODEC_CLK_IN / (NADC.MADC.AOSR)

     *        Options:

     *                       -> 84.672MHz = (3.528MHz  x 1 x 24.0)/1 --> For Fs = 44.1KHz

     *                       -> 92.160MHz = (3.840MHz  x 1 x 24.0)/1 --> For Fs = 48KHz

     *                                                     -> 44.1KHz = 84.672MHz / (3.5.128)

     *                                                     -> 48KHz = 92.160MHz / (3.5.128)

     *        Considerations:

     *                       -> MDAC * xOSR >= ResourceClass * 32

     *                                      - 5 * 128 (640) >= 8 * 32 (256)

     *                       -> 2.8MHz < xOSR x ADC_Fs < 6.758MHz

     *                                      - 128 * 44,100 = 5.644MHz

     *                                      - 128 * 48,000 = 6.144MHz

     *                       -> xOSR must be a multiple of 8 (48KHz High-Performance)

     *                                      -> xOSR = 64, for Low-Power Mode

     *                                      -> xOSR = 128, for High-Performance Mode

     */

   

    CodecPageSelect(1);

      CodecRegWrite(0x02, 0x00);

     

    CodecPageSelect(0);

      CodecRegWrite(0x04, 0x47);

      CodecRegWrite(0x05, 0x91);

     

      CodecRegWrite(0x06, 0x18);

      CodecRegWrite(0x06, 0x04);

     

      CodecRegWrite(0x07, 0x00);

      CodecRegWrite(0x08, 0x00);

     

      BTPS_Delay(20);

     

      CodecRegWrite(0x0B, 0x83);

        //CodecRegWrite(0x0B, 0x84);

     

      CodecRegWrite(0x0C, 0x85);

        //CodecRegWrite(0x0C, 0x82);

     

      CodecRegWrite(0x0D, 0x00);

      CodecRegWrite(0x0E, 0x80);

     

      CodecRegWrite(0x1B, 0xC0);

      CodecRegWrite(0x1C, 0x00);

      CodecRegWrite(0x3C, 0x02);

   

    CodecPageSelect(1);

      CodecRegWrite(0x01, 0x10);

      CodecRegWrite(0x0A, 0x00);

     

      CodecRegWrite(0x0C, 0x00);

         //CodecRegWrite(0x0C, 0x04);

     

      CodecRegWrite(0x16, 0x00);

      CodecRegWrite(0x18, 0x00);

     

      CodecRegWrite(0x09, 0x00);

          //CodecRegWrite(0x09, 0x20);

     

      CodecRegWrite(0x10, 0x40);

          //CodecRegWrite(0x10, 0x00);

     

      CodecRegWrite(0x2E, 0x00);

      CodecRegWrite(0x30, 0x10);

      CodecRegWrite(0x2D, 0x02);

   

   CodecPageSelect(0);

      CodecRegWrite(0x3F, 0x90);

      CodecRegWrite(0x41, 0x00);

      CodecRegWrite(0x40, 0x04); 

}

Thanks,

Christina

  • 0
    TI__Guru** 110125 points
    Hi Christina,

    I have reviewed your register settings and I found the following:
    You're setting P=1, R=1, J=4, D=0, NDAC=3, MDAC=5 and DOSR=128. Using BCLK=512kHz as input to the PLL it would be Fs = [512*10^3*((1*4.0)/1)]/[3*5*128] = 1.066kHz which is not good.
    I would recommend to set the following values: P=1, R=1, J=4, D=0, NDAC=1, MDAC=1 and DOSR=128 in order to get Fs = [512*10^3*((1*4.0)/1)]/[1*1*128] = 16kHz

    In addition I noticed that you're setting LJF and DAC data is picked from Left Channel only. Is your source system working according to this settings?

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators
  • 0 in reply to Ivan Salazar
    TI__Expert 6345 points

    Hi Ivan,

    Can we not use PLL, with just NDAC=MDAC=1, DOSR=32?

    We are referencing the design from MSPAudsink project below

    www.ti.com/.../bt-mspaudsink-rd

     

    Thanks,

    Christina

     

  • 0 in reply to Christina Lim
    TI__Guru** 110125 points
    Christina,

    It is recommended to use DOSR = 64 or 128, however this suggested setup (DOSR = 32) should work too.
    You could try this and evaluate the device operation.

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators