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TLV320ADC3101: Generating Master Clock from BCLK

Sadanori Kato
Guru 36540 points
Part Number: TLV320ADC3101

Hi,

Could TLV320ADC3101 support the 3-wire PCM ?
For the audio serial interface configurations, 3-wire PCM is mentioned in the application report however it isn't mentioned whether TLV320ADC3101 can support it or not.

http://www.ti.com/lit/an/slaa469/slaa469.pdf

Best regards,
Kato

  • 0
    TI__Guru 57800 points

    Hi, Kato-san,

    The TLV320ADC3101 is able to generate the required internal clocks using BCLK and the internal PLL, as depicted in the app note you are mentioning.

    Basically, BCLK should be selected as the source for the PLL, and PLL_CLK as the source for ADC_CLKIN. The dividers should be set accordingly to meet the clock specifications from the datasheet.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Guru 36540 points

    Hi Diego-san,

    Thank you for your prompt reply.
    I understood.

    Best regards,
    Kato