PCM1863: Calculation of PLL and other dividers for 8MHZ Input

Hi, Marc,

Please refer to the following coefficient values for the PLL and dividers setting.

• P=1
• R=1
• J=9
• D=2160

• DSP1_DIV= 8 6
• DCP2_DIV= 8 6
• ADC_DIV= 16 12

• PLL_SCK=6
• SCK_BCK=4
• BCK_LRCK=64

Regarding the startup sequence, the device starts operation expecting proper power supplies and clocks. By default, the part is in automatic-clock detection mode, so you need to configure the PLL and internal clock tree to make the device work. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

thanks for your reply. I tested it with the values you provided. We can hear the i2s audio on our receiver side. The clocks I measured are BCK=2MHZ, LRCK=31,24KHZ.

I have some additional questions:

1. Are the measured clock values correct? We expected output of LRCK=48KHZ and BCK = 48KHZ*64= 3,072MHZ.

2. In the datasheet it is mentioned that N should be multiple of 2. In your example, N = PLL_SCK*SCK_BCK*BCK_LRCK=1536. Is this correct?

3. How can I measure the internal pll out frequency?

4. In SLAS831C on page 29 the picture shows several Muxes inside the box "Master Mode Only". How can those muxes be configured (is it necessary)?

Thanks in advance

Marc

Hi, Marc,

I would like to mention that I made a typo on the values proposed before, The correct settings for the dividers should be 6, 6 and 12 respectively, I have fixed my previous response. Sorry for the confusion.

The values should be as you mention, 48KHz and 3.072MHz, please try with the correct divider values and check if there is any improvement.

The muxes inside the Master Mode box corresponds to registers CLK_DIV_PLL_SCK, CLK_DIV_SCK_BCK and CLK_DIV_BCK_LRCK.

I verified the divider values in the EVM and the device is able to generate correct clocks. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

you corrected the dividers for adc and dsp1/2 which don't have an impact on BCK and LRCK. I still measure LRCK=31,24KHZ and BCK=2MHZ.

Below is my init sequence.

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 0, 0xFF); // Reset
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 0, 0x00); // Page 0 auswählen
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 32, 0x5E); // auto clock detect off, pll is source for adc and dsp1/2

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 37, 0x05); // pll sck divider = 6
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 38, 0x03); // sck bck divider = 4
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 39, 0x3F); // bck lrck divider = 64

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 40, 0x01); // pll enable

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 41, 0x00); // P = 1
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 42, 0x00); // R = 1
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 43, 0x09); // J = 9
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 45, 0x08); // D = 0x08 (MSB)
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 44, 0x70); // D = 0x70 (LSB) -> complete value (2160=0x0870) is set when LSB is set!!

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 33, 0x05); // dsp1 divider = 6
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 34, 0x05); // dsp2 divider = 6
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 35, 0x0B); // adc divider = 12

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 6, 0x41); // adc1 input left = VINL1 single ended
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 7, 0x40); // adc1 input right = None
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 8, 0x40); // adc2 input left = None
TwiWriteReg(SLAVE_ADDRESS_PCM1863, 9, 0x40); // adc2 input right = None

TwiWriteReg(SLAVE_ADDRESS_PCM1863, 1, 0x50); // Gain 40dB

Greetings 

Marc

When I write 0x7E instead of 0x5E to register 32 (0x20), I get correct results. BCK =3,072MHZ and LRCK=48KHZ. I just changed MST_SCK_SRC from 0(SCK or XI) to 1 (BCK). But I don't understand why it works now. We use SCKI input for external 8 MHZ clock.

Hi, Mark,

Thanks for the feedback. There is a typo in the datasheet Register 32 value for MST_SCK_SRC, instead of "1: BCK" it should say "1: PLL (as in BCK PLL mode)". We are working to fix this in the next datasheet revision. So, for your application, writing a '1' bit 5 of register 32 is required to setup PLL output as the source to generate the BCK and LRCK clocks in Master mode.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

thanks for the information, everything works now! Just one additional question. We use analog micropone and have auto gain mode enabled. So max. gain (analog+digital) is 40dB (register1 = 0x50). For our application we need some more gain. Is there a way to get some additional gain in the pcm1863?

Greetings

Marc

Hi, Marc,

For the PCM1863, the maximum gain possible with the PGA is +40dB, however, the digital mixer PGA can add up to +18dB of additional gain to the audio signal. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Thanks for the quick response. That's what I was looking for. What is the correct sequence for writing/reading the mixer gain (CH1L)? Do I have to poll register 1 on page 1 for the device being ready? Where can I find information about the 4.20 number format? The link in the datasheet to SLAC663 is not valid. What register value represents +18dB mixer gain?

Greetings

Marc

Hi, Marc,

The sequence is specified in the datasheet, we improved the information about the DSP coefficient programming on the datasheet of the automotive version of this part, please take a look to PCM1863-Q1 datasheet as reference. Please refer to the following code example to setup a 18dB gain in CH1L mixer.

w 94 00 01
w 94 02 00
w 94 04 7f 17 af 00
w 94 01 01

As reference, You can use the PurePath Console GUI and EVM to easily monitor the correct sequence to write and read the mixing coefficient. You can download the calculator to convert from dB to the hexadecimal coefficient required from SLAC663.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer