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TLV320AIC3106: AIC3106 AGC problems

Part Number: TLV320AIC3106

Hello,

 

We are working with the TLV320AIC3106 Codec and have 2 problems with its AGC:

  1. When calibrating the AGC we found out that its output level (Digital output) is not constant along our audio frequency range (300Hz-3.5KHz). At the high end of the audio range, we achieved the assigned target level; at the low end the output level increased up to 5dB above the target level.

The CODEC assigned to work at 16K samples per second. We are also sampling the digital audio output at 16K samples per seconds and 24 bits per sample.

We designed the AGC to bring the audio signal to half of the full scale, +/- 4E6 (for 24 bits).

We set AGC registers to:

       Reg  26 : 0xA3

       Reg  27 : 0xA0

 We are not using the ADC 1’st order High Pass output digital filter

The audio signal sampled at LINE2L and it is set for differential mode operation.

The signal level inserted is 44 millivolt.

When inserting 1.5KHz signal, the DSP measure 4.1E6 positive and negative peaks.

When inserting 300Hz signal, the DSP measure 6.2E6 positive and negative peaks.

  1. Aliasing problem. Even very low level of input signal near 8KHz causes high amplitude “fuzzy” and noisy output signals. Although this frequency is outside of our audio range, some high frequency background signals can cause severe audio interferences.

 

Please advise us about the potential causes for both problems and preferred solutions. Is the main cause for the 1’st problem related to the AGC averaging method? Is both problems related to the relatively low sample rate that we are using to operate the CODEC?

 

Best Regards,

Shlomo

  • Hi, Shlomo,

    We will take a look at your questions. Do you have any capture of the digital output from the codec?. AGC should maintain the amplitude across the configured frequencies. Do you see any change when enabling the ADC's digital filter?. Can you share the clock setting of the device?. 

    The second issue seems related to the sampling rate as you mention as the internal clocking is derived from the Fsref frequency rather than the 16KHz sampling clock.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hello  Diego

    Thank you for your answer and very sorry for the delay to answer you.

    We are sampling the audio in 24 bits  so our maximum peak level is  +- 8 Mega .

    When agc is calibrated  with this regs vals:

    Reg  26 : 0xA3   ( we should  get  a target level of half the full scale about  +- 4 mega )

    Reg  27 : 0xA0

    The result measured from the  codec in some freqs are :

          200 Hz  =>  7.9  mega

          300 Hz  => 6.4  mega

          700 Hz =>  4.6 mega

         1000 hz => 4.26 mega

         2500 hz  =>  4.13 mega

    The codec is set as master .

    We already tried to use the ADC HP filter. We already realized that the above effect of higher target level at low frequency is much more relaxed. We would like to know why this problem exist so a HP filter is needed to work around it.

    To generate the  Fs   of codec we do not use the PLL path .

    The  formula :  Fs(ref) =  CLKDIV_IN / 128 * Q =  24.576 Mhz / 128 * 4 = 48000

                                Fs = Fs(ref) / 3 = 16000

    Part of the relevant reg are:

    Reg 1 = 0x80

    Reg 2 = 0x44

    Reg 3 = 0x20

    Reg 4 = 0x04

    Reg 5 = 0x00

    Reg 6 = 0x00

    Reg 7 = 0x0a

    Reg 8 = 0xc0

    Reg 101 = 0x01

    The series aliasing problem that we already seen at the ADC Out is suddenly disappeared! We cannot cause it to happen again! It is very good but we afraid that it can take place again… Did you have a possible explanation?

    Regards .