I'm trying to set up the chain as headline describe but don't get data output on PORTB. The _RDY_ signal never goes low either so it seems that the "Rate Estimator" doesn't finish.
I'm using MCLK of 24.576MHz.
I successfully set up DIR->PORTB (master mode) directly and get data out on PORTB. So I know the DIR part is producing data OK (I also get LOCK signal and RCKO for the DIR part).
This is my register settings:
SRC4392_REGWRITE(SRC4392_PAGE_SEL_REG, 0);
// PORT B set Philips I2S, master mode, SRC input => b0011 1001
SRC4392_REGWRITE(SRC4392_PORTB_REG1, 0x39);
// PORT B set MCLK clock source and divider=512, 48kHz => b0000 0011
SRC4392_REGWRITE(SRC4392_PORTB_REG2, 0x03);
// set MCLK as PLL1 clock source
SRC4392_REGWRITE(SRC4392_DIR_REG1, 0x08);
// enable RXCKO and div by 8
SRC4392_REGWRITE(SRC4392_DIR_REG2, 0x07);
// MCLK=24.576MHz => P=2, J=8, D=0
// b0010 0010
SRC4392_REGWRITE(SRC4392_PLL1_REG1, 0x22);
// b0000 0000
SRC4392_REGWRITE(SRC4392_PLL1_REG2, 0x00);
// b0000 0000
SRC4392_REGWRITE(SRC4392_PLL1_REG3, 0x00);
// set up SRC
// input DIR and use MCLK => b0000 0010
SRC4392_REGWRITE(SRC4392_SRC_REG1, 0x02);
// rest of SRC uses default settings...
// enable everything
SRC4392_REGWRITE(SRC4392_PWR_RST_REG, 0x3f);
