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TLV320AIC3254: miniDSP_A and miniDSP_D cycles limitations

stathisv70
Prodigy 60 points
Part Number: TLV320AIC3254

Hi all,

I am designing an application using the AIC3254 which involves capturing audio from the ADC, doing some signal processing and sending the output to the I2S interface. The settings for the ADC clock are MADC=2, NADC=1 and AOSR=128, to give a sample rate of 48KHz for the given input MCLK. These settings limit the max miniDSP_A cycles to 256.

After adding some additional blocks in PurePath Studio I seem to have run out of cycles and the project does not build anymore. I wonder if it is possible to split the processing load between miniDSP_A and miniDSP_D. I assumed that in order to do that miniDSP_D should be set to 256 cycles too and SynchMode enabled in the framework. However, PurePath Studio seems to have a low limit of 352 for the miniDSP_D cycles. Is there any way to use both miniDSPs and transfer data between them in my setup?

Thank you in advance for your help

  • 0
    TI__Guru 57800 points

    Hi, Stathisv,

    Welcome to E2E, Thanks for your interest in our products!.

    Can you please clarify the process flow you are using?, the number of cycles is limited when the framework selected is intended to be used with higher sampling rates.

    You can split the processing between both miniDSPs without issues, also, if you are not planning to change the miniDSP settings during the operation of the device, you can disable adaptive mode and get more processing power You can find more information regarding the cycles for each miniSDP in the following link.

    https://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/1098.aic3254-minidsp-d-cycles-and-minidsp-a-cycles 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 60 points

    Hi Diego,

    Thank you for your reply. Below is my PPS block diagram:

    My sample rate is 48 KHz. The 256 cycles limitation for miniDSP_A is clear to me since AOSR=128 and MADC=2. It agrees with your link too.

    What I do not understand is why PPS does not allow setting the cycles for miniDSP_D to anything less than 352. In order to enable SynchMode both miniDSPs need to have the same number of cycles.

    I am not able to disable Adaptive Mode because I need to be able to change to Volume Control.

    Best regards,

    Stathis

  • 0 in reply to stathisv70
    Prodigy 60 points
    Sorry, it looks like the PPS block diagram did not appear correctly.
    In any case I am using the AIC3254App8x4x framework, MonoDec4xIn for input, MonoI2S_Out for output. There are also a Volume, VAD and comparator blocks. The result is that 256 cycles are not enough.