Hi teams
I have some question about tlv320aic3268. My customer use tlv320aic3268 with no AD/DA ,it works well. But when he configure the AD/DA and run them, Nothing output for the PN. the configure code as
follow,Could you give us some advice?
/**********************************************************************************
WV_S32 EXT_3268_ADC_DAC_LOOP(EXT_3268_DEV_E * pDev);
**********************************************************************************/
WV_S32 EXT_3268_ADC_DAC_LOOP(EXT_3268_DEV_E * pDev)
{
EXT_3268_Sel(pDev ); //sel IIC bus
usleep(100000);
// Software Reset
EXT_3268_Write(pDev,0,0);
EXT_3268_Write(pDev,0x7f,0);
EXT_3268_Write(pDev,0x01,0x01);
usleep(100000);
//FIFO Configuration
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x7f ,0x78);//Select Book 120
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x32 ,0x80);//Enable DAC FIFO
EXT_3268_Write(pDev,0x7f ,0x64);//Select Book 100
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x32 ,0x80);//Enable ADC FIFO
EXT_3268_Write(pDev,0x7f ,0x00);//Select Book 0
// Power and Analog Configuration
EXT_3268_Write(pDev,0x00,0x04);//Select Page 4
EXT_3268_Write(pDev,0x77,0xc0);//Disable miniDSP power-up sync with ASI
// EXT_3268_Write(pDev,0x77,0x00);//Enable miniDSP power-up sync with ASI
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x01,0x00);//Disable weak AVDD to DVDD connection, make analog supplies available
//EXT_3268_Write(pDev,0x7a,0x05);// 1 Chip-Reference will be force-fully powered-up
// Signal Processing Settings
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x0d,0x00);//# Program DOSR = 128
EXT_3268_Write(pDev,0x0e,0x80);//# Program DOSR = 128
EXT_3268_Write(pDev,0x14,0x80);//Program AOSR = 128
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x03,0x08);//PTM_P1
EXT_3268_Write(pDev,0x04,0x08);//PTM_P1
// Clock configuration
// MCLK = 12.288 MHz, BCLK = 3.072 MHz, WCLK = 48 kHz
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x04,0x00); //Set DAC_CLKIN as MCLK -- default not mandatory to program
EXT_3268_Write(pDev,0x12,0x81); //NADC = 1
/*
EXT_3268_Write(pDev,0x04,0x33); //Set DAC/ADC_CLKIN as PLL_CLK
EXT_3268_Write(pDev,0x05,0x00); //Set PLL_CLKIN = MCLK
EXT_3268_Write(pDev,0x06,0x91); //P and R
EXT_3268_Write(pDev,0x07,0x07); //J
EXT_3268_Write(pDev,0x08,0x08); //D msb
EXT_3268_Write(pDev,0x09,0xce); //D msb
EXT_3268_Write(pDev,0x12,0x88); //NADC = 1
//*/
EXT_3268_Write(pDev,0x13,0x82); //MADC = 2
EXT_3268_Write(pDev,0x14,0x80); //Program the OSR of ADC to 128,
//ADC_FS = ADC_MOD_CLK / AOSR = 6.144MHz / 128 = 48kHz
EXT_3268_Write(pDev,0x0b,0x81); //NDAC = 1
EXT_3268_Write(pDev,0x0c,0x82); //MDAC = 2
EXT_3268_Write(pDev,0x0d,0x00); //Program the OSR of DAC to 128 to get
EXT_3268_Write(pDev,0x0e,0x80); //DAC_FS = DAC_MOD_CLK / DOSR = 6.144MHz / 128 = 48kHz
//Audio Serial Interface Routing Configuration - Audio Serial Interface #1
//ASI #1 playback mast?
EXT_3268_Write(pDev,0x00,0x04);//Select Page 4
EXT_3268_Write(pDev,0x01,0x00);//I2S mode, 16-bit
EXT_3268_Write(pDev,0x0a,0x24);//Route ASI#1 WCLK and BCLK to WCLK1 pin and BCLK1 pin
//D7-D5 001: WCLK1 pin is Word Clock output from ASI1
//D4-D2 001: BCLK1 pin is Bit Clock output from ASI1
EXT_3268_Write(pDev,0x08,0x50);//Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x3c,0x01); //Set the DAC Mode to PRB_P1
EXT_3268_Write(pDev,0x3D,0x01); //Set the ADC Mode to PRB_P1
//EXT_3268_Write(pDev,0x3f,0xc2);//Power up the Left and Right DAC Channels with route the Primary
//ASI's left channel data to Left DAC and right channel to Right DAC
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x3D,0x00);//ADC Analog programmed for PTM_R4
EXT_3268_Write(pDev,0x00,0x04);//Select Page 4
EXT_3268_Write(pDev,0x76,0x36);//Loop back
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
//EXT_3268_Write(pDev,0x51,0xc0);//Power-up ADC Channel
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x23,0x30);//
EXT_3268_Write(pDev,0x09,0x00); // HP Sizing = 100%
EXT_3268_Write(pDev,0x4d,0x01); // HP Sizing = 100%
EXT_3268_Write(pDev,0x08,0x00);//Full chip CM = 0.9V
// EXT_3268_Write(pDev,0x03,0x00);//PTM_P3/P4
// EXT_3268_Write(pDev,0x04,0x00);//PTM_P3/P4
EXT_3268_Write(pDev,0x09,0x00); // HP Sizing = 100%
EXT_3268_Write(pDev,0x4d,0x01); // HP Sizing = 100%
EXT_3268_Write(pDev,0x1f,0x00); // Headphone in Ground-centered Mode, HPL Gain=0dB ?????????????
EXT_3268_Write(pDev,0x20,0x80); //HPR To have same gain as HPL, set to 0dB
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x11,0x0c); // Power-on left and right analog mixers (MAL, MAR)
EXT_3268_Write(pDev,0x1b,0xf3); //Enable DAC to HPL/R and power-up HPL/R MAL/R // ?
usleep(40000);
//EXT_3268_Write(pDev,0x34,0x20);//Connect IN2L(Mic_In) to PGA with 20k input //?
//EXT_3268_Write(pDev,0x37,0x20);//Connect IN2R(Mic_In) to PGA with 20k input //?
EXT_3268_Write(pDev,0x36,0x80);//Set Left common mode input resistor to 20k
EXT_3268_Write(pDev,0x39,0x02);//Set Right common mode input resistor to 20k
EXT_3268_Write(pDev,0x12,0x00);//Connect left PGA to left analog mixer
EXT_3268_Write(pDev,0x13,0x00); //Connect right PGA to right analog mixer
EXT_3268_Write(pDev,0x3b,0x00); // Unmute left PGA
EXT_3268_Write(pDev,0x3c,0x00); // Unmute right PGA
//set input
WV_U8 regP1R52;
WV_U8 regP1R53;
WV_U8 regP1R55;
WV_U8 regP1R56;
regP1R52 = (pDev-> liCtl[0] & 0X03) << 6;
regP1R52 |= (pDev-> liCtl[1] & 0X03) << 4;
regP1R52 |= (pDev-> liCtl[2] & 0X03) << 2;
regP1R53 = (pDev-> liCtl[3] & 0X01) << 5;
regP1R55 = (pDev-> liCtl[0] & 0X03) << 6;
regP1R55 |= (pDev-> liCtl[1] & 0X03) << 4;
regP1R55 |= (pDev-> liCtl[2] & 0X03) << 2;
regP1R56 = (pDev-> liCtl[3] & 0X01) << 5;
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x7f ,0x00);//Select Book 0
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x34,regP1R52);//Set Left common mode input resistor to 20k
EXT_3268_Write(pDev,0x35,regP1R53);//Set Left common mode input resistor to 20k
EXT_3268_Write(pDev,0x37,regP1R55);//Set right common mode input resistor to 20k
EXT_3268_Write(pDev,0x38,regP1R56);//Set right common mode input resistor to 20k
EXT_3268_Write(pDev,0x00,0x01);//Select Page 1
EXT_3268_Write(pDev,0x7a,0x05);// 1 Chip-Reference will be force-fully powered-up
usleep(2000000);
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_Write(pDev,0x40,0x00); // # Unmute the DAC digital volume control
EXT_3268_Write(pDev,0x52,0x00);//Unmute ADC channel and Fine Gain = 0dB
//EXT_3268_Write(pDev,0x3f,0xc0);//Power up the Left and Right DAC Channels with route the Primary
//ASI's left channel data to Left DAC and right channel to Right DAC
usleep(40000);
//EXT_3268_Write(pDev,0x51,0xc0);//Power-up ADC Channel
// EXT_3268_Write(pDev,0x51,0xea);//Power-up ADC Channel
usleep(40000);
EXT_3268_Write(pDev,0x00,0x00);//Select Page 0
EXT_3268_DeSel(pDev ); //desel IICbus
return WV_SOK;
}
