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TLV320DAC3100-Q1: TLV320DAC3100-Q1

Part Number: TLV320DAC3100-Q1

Hello,

Customer is evaluating TLV320DAC3100-Q1 and they are seeing weird HP output waveform.

I2S input is 16-bit, Fs = 44.1kHz, MCLK = 11.2896MHz and register setting follows I2C script below. Can anyone help on this?

# (a) Program PLL clock dividers P, J, D, R (if PLL is used)

#

# PLL_clkin = MCLK,codec_clkin = PLL_CLK

w 30 04 03

# J = 8

w 30 06 08

# D = 0000, D(13:8) = 0, D(7:0) = 0

w 30 07 00 00

#

# (b) Power up PLL (if PLL is used)

# PLL Power up, P = 1, R = 1

w 30 05 91

#

# (c) Program and power up NDAC

#

# NDAC is powered up and set to 8

w 30 0B 88

#

# (d) Program and power up MDAC

#

# MDAC is powered up and set to 2

w 30 0C 82

#

# (e) Program OSR value

#

# DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128

w 30 0D 00 80

#

# (f) Program I2S word length if required (16, 20, 24, 32 bits)

# and master mode (BCLK and WCLK are outputs)

#

# mode is i2s, wordlength is 16, slave mode

w 30 1B 00

# (g) Program the processing block to be used

#

# Select Processing Block PRB_P11

w 30 3C 0B

w 30 00 08

w 30 01 04

w 30 00 00

#

# (h) Miscellaneous page 0 controls

#

# DAC => volume control thru pin disable

w 30 74 00

  • Hi Sam,

    After looking at your script, I don't find where do you power up the Headphone driver and DAC. Also I can't find command to route DAC to output driver.
    Could you try the following to see if it works better? I added some commands at the bottom:
    # (a) Program PLL clock dividers P, J, D, R (if PLL is used)
    #
    # PLL_clkin = MCLK,codec_clkin = PLL_CLK
    w 30 04 03
    # J = 8
    w 30 06 08
    # D = 0000, D(13:8) = 0, D(7:0) = 0
    w 30 07 00 00
    #
    # (b) Power up PLL (if PLL is used)
    # PLL Power up, P = 1, R = 1
    w 30 05 91
    #
    # (c) Program and power up NDAC
    #
    # NDAC is powered up and set to 8
    w 30 0B 88
    #
    # (d) Program and power up MDAC
    #
    # MDAC is powered up and set to 2
    w 30 0C 82
    #
    # (e) Program OSR value
    #
    # DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
    w 30 0D 00 80
    #
    # (f) Program I2S word length if required (16, 20, 24, 32 bits)
    # and master mode (BCLK and WCLK are outputs)
    #
    # mode is i2s, wordlength is 16, slave mode
    w 30 1B 00
    # (g) Program the processing block to be used
    #
    # Select Processing Block PRB_P11
    w 30 3C 0B
    w 30 00 08
    w 30 01 04
    w 30 00 00
    #
    # (h) Miscellaneous page 0 controls
    #
    # DAC => volume control thru pin disable
    w 30 74 00
    # --------------------------------------------------------------- page 1 is selected
    w 30 00 01
    # De-pop, Power on = 800 ms, Step time = 4 ms
    w 30 21 4e
    # HPL and HPR powered up
    w 30 1f c2
    # LDAC routed to HPL, RDAC routed to HPR
    w 30 23 44
    # HPL unmute and gain 1db
    w 30 28 0e
    # HPR unmute and gain 1db
    > 0e
    # No attenuation on HP
    w 30 24 00
    w 30 25 00
    # --------------------------------------------------------------- page 1 is selected
    w 30 00 00
    # POWERUP DAC left and right channels (soft step disable)
    w 30 3f d6
    # UNMUTE DAC left and right channels
    > 00
    #

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators