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TLV320AIC3106: Processing Delay

Part Number: TLV320AIC3106

Hello,

How long does it take for Codec Data In to make its way to the DAC output? and ADC input to make it to the Codec Data Out?

Say the I2S bus holds data in Sample Frame 0. That data is shifted into the Codec during Frame 0. Does the 21/fs interpolation time start at the WCLK pulse of Frame 1? Finishes in frame21? DAC output gets updated at WCLK pulse of Frame 22?

Similarly, if there is an analog voltage present and stable at the ADC inputs at the time of the WCLK pulse in frame 0. 17/fs starts in Frame 0, decimation is finished in Frame 16. Does the ADC result get shifted onto the I2S bus in Frame 17?

Digital word in (Frame 0) --> DAC output --> ADC input --> Digital word out (Frame 41)?   18 + 23?

Thanks for your help,
Curt

  • Hi, Curtis,

    The total group delay of the device blocks is 21/Fs for the DAC and 17/Fs for the ADC. So, for a complete path from DIN to DOUT, the total group delay would be (21+17)/Fs.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer