TAS2521: register settings for TAS2521

Hi Priyan,

You can use the example configuration from the device GUI.
Speaker script:
# Playback Class-D
# Page switch to Page 0
W 30 00 00
# Assert Software reset
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up.
W 30 02 00
# Page switch to Page 0
W 30 00 00
# Dac Instruction programming PRB #1
W 30 3c 01
# CODEC_CLKIN=MCLK.MCLK should be 12.288MHz
W 30 04 00
# Codec Interface control Word length = 16bits.BCLK&WCLK inputs.I2S mode.
W 30 1b 00
# Data slot offset 00
W 30 1c 00
# DAC NDAC Powered up, NDAC=1
W 30 0b 81
# DAC MDAC Powered up, MDAC=2
W 30 0c 82
# DAC OSR(9:0)-> DOSR=128
W 30 0d 00
# DAC OSR(9:0)-> DOSR=128
W 30 0e 80
# Only LDAC powered up.Dac path setup LDAC data Mono of LDAC and RDAC. RDAC data disabled.Soft step 1 per Fs.
W 30 3f B0
# DAC volume for Left channel not muted.Right DAC muted.
W 30 40 04
# LDAC digital gain 0dB
W 30 41 00
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on
W 30 01 10
# Output common mode for DAC set to 0.9V (default)
W 30 0a 00
# LDAC AFIR is 6th order FIR filter and Powered up.
W 30 03 00
# SPKL attn. Gain =0dB
W 30 2E 00
# SPKL driver PGA Gain=6.0dB
W 30 30 10
# SPK OSCP enabled , OCP Degltich=4, OTP enabled , OTP Deglitch=5
W 30 52 00
# SPK powered up
W 30 2D 02

Headphone script:
# Playback HP
# Page switch to Page 0
W 30 00 00
# Assert Software reset
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up.
W 30 02 00
# Page switch to Page 0
W 30 00 00
# Dac Instruction programming PRB #1 for Mono routing.
W 30 3C 01
# CODEC_CLKIN=MCLK.MCLK should be 12.288MHz
W 30 04 00
# Codec Interface control Word length = 16bits.BCLK&WCLK inputs.I2S mode.
W 30 1b 00
# Data slot offset 00
W 30 1c 00
# DAC NDAC Powered up, NDAC=1
W 30 0b 81
# DAC MDAC Powered up, MDAC=2
W 30 0c 82
# DAC OSR(9:0)-> DOSR=128
W 30 0d 00
# DAC OSR(9:0)-> DOSR=128
W 30 0e 80
# Only LDAC powered up.Dac path setup LDAC data Mono of LDAC and RDAC. RDAC data disabled.Soft step 1 per Fs.
W 30 3f B0
# DAC volume for Left channel not muted.Right DAC muted.
W 30 40 04
# LDAC digital gain 0dB
W 30 41 00
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on
W 30 01 10
# Output common mode for DAC set to 0.9V (default)
W 30 0a 00
# LDAC AFIR is 6th order FIR filter and Powered up.
W 30 03 00
# Power up HPL
w 30 09 20
#Signal to HPL
w 30 0c 04
# unmute HPL
w 30 10 00

Best regards,
-Ivan Salazar
Audio Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

This gives audio output , but I hear a small disturbing background noise. My I2S MCLK is 11.29 MHz. The above settings says it shall be 12.28 MHz.
Can you please give me the settings for my MCLK (11.29 MHz) or can you guide me using the codec control software to generate the settings. I, but dont have the EVM.

Hi Priyan,

For MCLK = 11.29MHz you can use the following values:
P = 1
R = 1
J = 7
D = 6188
NDAC = 7
MDAC = 2
DOSR = 128

So you will need to modify the script with the following lines:
w 30 04 03
w 30 05 91
w 30 06 07
w 30 07 18
w 30 08 2C
w 30 0B 87
w 30 0C 82
w 30 0D 00
w 30 0E 80

Best regards,
-Ivan Salazar
Audio Applications Engineer - Low Power Audio & Actuators

Hi Ivan

Is below code correct for 48kHZ, 16 bit per sample, mono audio with 11.29 MHZ MCLK for HeadPhone alone?

Format: WriteRegisterData(Register, Data)

WriteRegisterData(0x00,0x00);
WriteRegisterData(0x01,0x01);
WriteRegisterData(0x00,0x01);

WriteRegisterData(0x02,0x00);
WriteRegisterData(0x00,0x00);
WriteRegisterData(0x3C,0x01);
WriteRegisterData(0x04,0x03);
WriteRegisterData(0x05,0x91);
WriteRegisterData(0x06,0x07);
WriteRegisterData(0x07,0x18);
WriteRegisterData(0x08,0x2C);

WriteRegisterData(0x1B,0x00);
WriteRegisterData(0x1C,0x00);
WriteRegisterData(0x0B,0x87);
WriteRegisterData(0x0C,0x82);
WriteRegisterData(0x0D,0x00);
WriteRegisterData(0x0E,0x80);
WriteRegisterData(0x3F,0xB0);
WriteRegisterData(0x40,0x04);
WriteRegisterData(0x41,0x00);

WriteRegisterData(0x00,0x01);
WriteRegisterData(0x01,0x10);
WriteRegisterData(0x0A,0x00);
WriteRegisterData(0x03,0x00);

WriteRegisterData(0x09,0x20);
WriteRegisterData(0x0C,0x04);
WriteRegisterData(0x10,0x00);

I am still having some background noise? Is there any feature to test any know pattern within the TAS2521 DAC ?

Priyan,

You mention mono audio. What channel are you using to send audio data? You're using I2S format right?
Perhaps you can change Page 0 Reg 0x3F bits D5:D4 to 01 or 10

Best regards,
-Ivan Salazar
Audio Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

Yes, I am using I2S format and mono audio with 16bit per sample. Audio is sent over Left Channel.

The I2S MCLK, if Sampling frequency is 48 kHZ is 6.157 MHz.
The I2S MCLK, if Sampling frequency is 44.1 kHZ is 5.63 MHz.

Sorry for the confusion caused.

Can I get Headphone settings alone for now for both 48kHZ and 44.1kHZ Sampling rates separately? I shall try both and evaluate the performance.

Priyan,

MCLK = 6.157MHz and 5.63MHz are too low frequencies to be used. Using this frequencies won't allow the device to comply with the constraints explained in the Applications Reference Guide (Page 33).
Is it possible for your application to set a higher MCLK frequency?

Best regards,
-Ivan Salazar
Audio Applications Engineer - Low Power Audio & Actuators