TLV320AIC3105: TLV320AIC3105 MIC capture

Hi Bruce,

Can you clarify, you are saying that you are able to set up the device, and it functions as you expect, but then you mute the PGA and it disconnects Line1L from the PGA?

Regarding your register writes, I suggest going line by line, and comment what each write is doing. this could help you find any errors there. if you don't find any errors, please repost the commented register writes.
best regards,
-Steve Wilson

Hi Steve,

Thanks for your quick response.

No, I set up TLV320AIC3105 to capture the sound from MIC1L/LINE1L and save the captured data in a file, but it is not working. I only get some garbage data in the file. Below is the register setting sequence. I have checked and tested many times, but can not find which one is wrong or missing.

Register 2: 0x00 //ADC fS = fS(ref)/1, DAC fS = fS(ref)/1
Register 3: 0x20 //PLL is disabled, Q=4
Register 7: 0x0A //fS(ref) = 48 kHz, left-ADC data path for left-channel, right-ADC for right-channel.
Register 8: 0xC0 //BCLK, WCLK are outputs (master mode)
Register 9: 0x00 //I2S mode, 16 bits
Register 10, 0x00 //Data offset=0
Register 12: 0x50 //Left-ADC, right-ADC HPF -3-dB frequency=0.0045 x ADCfs
Register 15: 0x7F //Left-ADC PGA is not muted, gain=59.5dB
Register 16: 0x7F //Right-ADC PGA is not muted, gain=59.5dB
Register 19: 0x04 //LINE1L to Left-ADC control register, gain=0dB, Left-ADC channel is powered up.
Register 22: 0x04 //LINE1R to right ADC control register, gain=0dB, right-ADC channel is powered up.
Register 25: 0xC6 //MICBIAS control register, MICBIAS output is connected to AVDD.
Register 37: 0xC0 //Left DAC and right DAC are powered.
Register 41: 0x00 //DAC output switching control register, left-DAC output selects DAC_L1, right-DCA output selects DAC_R1
Register 43: 0x00 //Left-DAC digital volume control register, left DAC channel is not muted, gain=0dB
Register 46: 0x00 //PGA_L to HPLOUT volume control register, PGA_L is not routed to HPLOUT.
Register 47: 0x80 //DAC_L1 is routed to HPLOUT

Register 101: 0x01 //CODEC_CLKIN uses CLKDIV_OUT
Register 102: 0x02 //CLKDIV_IN uses MCLK

I also tried test with AGC turned on and without AGC turned on, it is not working either. Here are register settings:

Register 26: 0x80 //Left AGC is enabled
Register 27: 0xFE //Left-AGC maximum gain allowed is 59.5dB
Register 28: 0x3F //hysteresis=1dB, left-AGC noise threshold= -90dB, clip stepping enable.
Register 34: 0x12 //left-AGC noise gate debounce=1ms


Regards,
Bruce

I don't see a R51 write. The HPLOUT block is muted and not powered up by default.

So Register 51: 0x0F

are you going to use HPLOUT and HPLCOM as a differential output? or will you be using HPLOUT as a Single ended output?

I only ask because you would have to do enable the HPLCOM block too if it is differential.

what is your MCLK frequency? it would appear that it is 24.576 based on your Q-Value and Fs, but I just want to make sure.

-Steve

Hi Steve,

Thanks for your help.

Yes, Register 51 should be set to 0x0F. I am using HPLOUT as a single ended output and MCLK is 24.576MHz.

Regards,

Bruce

No problem bruce, still no output though?

you mentioned that you are getting garbage in a file, are you talking about the I2S output?

Hi Steve,

Thanks a lot for your help.

Yes, I am trying to capture the sound from tlv320aic3105 MIC1L/LINE1L, AM335x host saves the data in the file from I2S output. I still cannot get the sound data in the file.

Regards,

Bruce

 

Hi Bruce,

Are you getting good output on HPLOUT?

best regards,
-Steve

Hi Steve,

Output on HPLOUT is good.

Regards,
Bruce

bruce, I sent you a connection request, can you send me a block diagram or schematic of your application? I would be interested to see what device you are connecting the Dout to.

-Steve