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TPA3131D2: TDA3131 datasheet clarification

Part Number: TPA3131D2

1. From the TDA3131 datasheet and EVM schematic it seems that the FAULT is an open drain output, so it can be pulled up to 3.3V or 2.5V instead of the PVCC. If this is correct - what would be the recommended pull-up resistors value? I guess my question is how much current this output can safely sink.

2. Is the circuit on the Figure 24 in datasheet correct? Why there are two 100K resistors connected in parallel from FAULT to PLIMIT/GVDD/GAIN/SLV which are tied together and then another 100K to the transistor's base?  It seems like transistor will be always on since it is connected to GVDD which is an internal LDO output. State of the FAULT output would not affect the voltage on that node - even when the FAULT is in the LOW state, it would present a very light 50K load for the LDO (about 140uA of current). Am I missing something here? 

3. Would it be possible to have TI engineer to check my schematic and if yes, how should I arrange that?

  • Hi Anushavan,

    I think 3.3V puii-up can be used for it, but 2.5V seems a little lower. Because the MIN of the High-level input voltage on SDZ/MUTE is 2V, and 2.5V is very close to it. 3.3V pull-up makes auto recovery/MUTE work normally by connecting SDZ pin to FALUT pin. The current on FAULT pin could be mA level according to our designer. We recommend to use more than 10K Ohm pull-up resistor on FAULT pin for 3.3V.

    Very sorry for the confusion. Your understanding is correct. There is some typo in this SCH in the datasheet. Please follow the SCH in TPA3131D2 EVM design for your reference.

    Please attach your SCH in the reply, I will help to review. If you don't want to expose it here, please close this question in E2E send me email shawn-zheng@ti.com We could communicate off-line.

    Best regards,

    Shawn Zheng

       

  • Hi Shawn,

    Thank you very much for your quick and detailed response. I'll send you my schematic page shortly via email.

    Best regards

    Anush