1. From the TDA3131 datasheet and EVM schematic it seems that the FAULT is an open drain output, so it can be pulled up to 3.3V or 2.5V instead of the PVCC. If this is correct - what would be the recommended pull-up resistors value? I guess my question is how much current this output can safely sink.
2. Is the circuit on the Figure 24 in datasheet correct? Why there are two 100K resistors connected in parallel from FAULT to PLIMIT/GVDD/GAIN/SLV which are tied together and then another 100K to the transistor's base? It seems like transistor will be always on since it is connected to GVDD which is an internal LDO output. State of the FAULT output would not affect the voltage on that node - even when the FAULT is in the LOW state, it would present a very light 50K load for the LDO (about 140uA of current). Am I missing something here?
3. Would it be possible to have TI engineer to check my schematic and if yes, how should I arrange that?