Hi,
We are trying to set this chip up properly to communicate with our FPGA. We've got the I2C communication working between our FPGA and the TLV320DAC3120. We also can see on an oscilloscope that our I2S output signals are correct. We want the TLV320DAC3120 to be configured as a slave device so that BCLK and WCLK are inputs. MCLK is not connected to anything.
I2S BCLK - 1.4112 MHz
WCLK - 44.1 kHz
The registers we write to and their values are listed below.
PX_RX = Page number X followed by Register number X
P0_R0 = 0 ( default is page 0 but go to page 0 in case TLV320DAC3120 hasn't been powered down )
P0_R1 = 1 ( software reset )
Delay for at least 1 ms
P0_R4 = 0x07 ( BCLK for PLL_CLKIN and PLL_CLK for CODEC_CLKIN
P0_R5 = 0x96 ( PLL is powered up, P = 1, R-VAL = 6 )
Delay for at least 10 ms
P0_R6 = 0x0A ( J-VAL = 10 )
P0_R7 = 0x00 ( D-VAL MSB = 0 )
P0_R8 = 0x00 ( D-VAL LSB = 0 )
P0_R11 = 0x85 ( NDAC_VAL = 5 and NDAC divider is powered up )
P0_R12 = 0x83 ( MDAC_VAL = 3 and MDAC divider is powered up )
P0_R13 = 0x00 ( DOSR MSB = 0 )
P0_R14 = 0x80 ( DOSR LSB = 128 )
P0_R25 = 0x03 ( CDIV_CLKIN = PLL_CLK )
P0_R26 = 0x81 ( CLKOUT divider M = 1 )
P0_R27 = 0x00 ( I2S, 16-bit word length, BCLK is input, WCLK is input )
P0_R51 = 0x10 ( GPIO1 output = CLKOUT output )
P0_R63 = 0x94 ( DAC is powered up, DAC data path = left data, Reserve bits, DAC channel volume control soft-stepping is enabled for one step per sample period )
P0_R64 = 0x04 ( DAC not muted )
P0_R65 = 0x00 ( DAC digital gain = 0 dB )
P0_R0 = 0x01 ( switch to page 1 )
P1_R32 = 0x86 ( Class-D output driver is powered up, Reserve bits )
P1_R35 = 0x40 ( DAC is routed to the mixer amp )
P1_R38 = 0x80 ( Analog vol control output is routed to class-D output driver, volume = 0 dB )
P1_R42 = 0x04 ( Gain = 6 dB, class-D driver is not muted )
P3_R16 = 0x08 ( internal osc is used, divided by 8 for ~1 MHz delay timer )
By these settings we should see the PLL_CLK on GPIO1 and all I see is the output is held high. If i route BCLK to GPIO1 and M = 1 then I'll see the clock coming out is exactly the same as BCLK coming in which is good. But for some reason it appears the PLL block doesn't get powered on. Even though in P0_R5 bit D7 = 1.
To further test this theory we connected BCLK to CODEC_CLKIN instead of PLL_CLK to see if we could generate DAC_CLK using NDAC and DAC_MOD_CLK using MDAC. So connecting DAC_CLK to GPIO1 we did see BCLK / NDAC as output so we know that NDAC is powered. Then we connected DAC_MOD_CLK to GPIO1 to test if MDAC is powered and we saw that the output clock was equal to BCLK/( NDAC * MDAC ) which is correct.
With BCLK still as the source of CODEC_CLK we tried sending some data just to see if we could get garbage on the output but we did not.
There's probably just some setting I'm missing or something. Does anybody know what the missing piece is?
EDIT: For anyone with a similar issue make sure you have HPVDD and HPVSS even if you're not using headphone out. This is the reason why we couldn't get our PLL to work.
