Hi all,
In the past we have used the TAS5756M succesfully with 4-wire I2S (I2S with MCLK).
In another design I'm working on, we would like to use the TAS device again, however this time there is only a 3-wire I2S available from the source. So I mean: dataline, wordclock (LRCKL) and serial bitclock (SCLK); no MCLK.
It seems this is possible with the TAS by generating our own MCLK from the PLL from the SCKL, right?
Another thread handles this as well but it seems the topic starter handled this further with a Skype-call, so I don't know the outcome.
https://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/t/625754?tisearch=e2e-sitesearch&keymatch=three%20wire%20PCM%20PLL
Hence my new topic.
My question is: how do we configure the PLL to generate an internal MCLK for the TAS, based on the SCLK.
I understand the clock distribution tree more or less (fig.61), but I'm confused by the description under 8.3.3.4.
Under 8.3.3.4.2.1 it's stated that PLLCKIN*K*R/P (so basically PLLCK, right?) has to be within a range of 64-100MHz.
Now let's use 48kHz 16bit audio, which has a bitclock of 3.072MHz and normally (image there was a MCLK) a MCLK of 24.576MHz.
So with the PLL we want to generate the absent 24.576MHz, but this is not within it's limits, is it? So I assume we need to generate a higher PLLCK and then use the clockdividers in the clock tree to reduce it to 24.576MHz, is this correct?
Further, I'm wondering on how exactly to determine the coefficients R, J, D and P for the formula. I tought I can use the recommended values from table 6, but this doesn't work out.
I could use the following values: R=2, J=4, D=0, P=1, which makes a PLLCK of 24.576MHz when PLLCKIN = SCLK = 3.072MHz, but this violates the earlier stated range of 64-100MHz and also violated the recommended values in table 6.
I'm really confused. Could someone point out just what the PLL-coefficients should be for 48kHz 16bit audio and why?
So to recap: no MCLK, but PLL generated clocks from SCLK.
Thanks in advance,
Kind regards
Julien Roels
