TLV320DAC3203: digital microphone (PDM) to Headphone output (II)

Hi,

What do you mean by BCLK and PDMCLK input is not provided by data sheet?
What are your clock signal frequencies? Are you using digital or analog input along with the digital mic input?
What are your current register settings?

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi,

What do you mean by BCLK and PDMCLK input is not provided by data sheet?

Please see the above graph, it is page 21 data sheet.

The outline indicate TLV320DAC3203 provide user using GPIO and MISO as clock for Dmic. (No BCLK).

Beside, in my application, I set MISO to be the PDM clock output to my digital microphone.

The previous thread using BCLK as PDM clock is not right.

What are your clock signal frequencies? Are you using digital or analog input along with the digital mic input?

In my application, I use digital microphone(PDM) .No analog input. I want 2.048MHz as PDM clock. So I set TLV320DAC3203 MISO pin as 

digital microphone clock output.

What are your current register settings?

Basically is the same to previous thread. I just do not what to use BCLK as PDM clock.
Beside, I don't know why loopback shoud enable in previous thread. Not clear what is it for?

{0x00, 0x00}, // 0. Initialize to page 0
{0x01, 0x01}, // 1. Initialize the device through software reset
{0x04, 0x03}, // 2. Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK  (I use 4MHz quartz crystal unit)
{0x05, 0x94}, // 3. Power up pll, set pll divider P=1 and pll divider R=4
{0x06, 0x07}, // 4. Set pll divider J=7
{0x07, 0x00}, // 5. Set pll divider D=0000
{0x08, 0x00}, // 6.
{0x12, 0x82}, // 7. Power up and set NADC divider = 2
{0x13, 0xb4}, // 8. Power up and set MDAC divider = 52 
{0x14, 0x40}, // 9. Set AOSR = 64
{0x0b, 0x82}, // 10. Power up and set NDAC divider = 2
{0x0c, 0xb4}, // 11. Power up and set MDAC divider = 52
{0x0d, 0x40}, // 12. Set DOSR = 64
{0x1d, 0x24}, // 13. Enable loopback, BDIV_CLKIN = DAC_CLK 
{0x1e, 0xb6}, // 14. Power up and set BCLK N divider = 54
{0x19, 0x03}, // 15. CDIV_CLKIN = PLL_CLK
{0x1a, 0xed}, // 16. Power up and set CLKOUT M divider = 109
{0x21, 0x03}, // 17.
{0x1b, 0x0d}, // 18. Set the word length of audio interface to 16 bits, audio interface to I2S
{0x3c, 0x01}, // 19. Set the DAC mode to PRB_P1
{0x00, 0x01}, // 20. Select page 1
{0x01, 0x08}, // 21. Disable internal crude AVdd in presence of external AVdd supply
{0x02, 0x00}, // 22. Enable master analog power control
{0x7b, 0x01}, // 23. Set the REF charging time to 40ms
{0x0a, 0x00}, // 24. Set the input common mode to 0.9V and output common mode for headphone to input common mode
{0x0c, 0x0c}, // 25. Route left DAC & INL to HPL
{0x0d, 0x0c}, // 26. Route right DAC & INR to HPR
{0x03, 0x00}, // 27. Set the DAC PTM mode to PTM_P3
{0x04, 0x00}, // 28.
{0x10, 0x00}, // 29. Set the HPL gain to 0dB
{0x11, 0x00}, // 30. Set the HPR gain to 0dB
{0x14, 0x29}, // 31. HP soft stepping settings for optimal pop performance at power up. Rpop used is 6k with N = 6 & soft step = 20usec
{0x09, 0x30}, // 32. Power up HPL and HPR drivers
{0x00, 0x00}, // 33. Select page 0
{0x37, 0x0e}, // 34. Configure MISO as clock output for digital microphone
{0x51, 0xdc}, // 35. Power up left ADC and right ADC. Enable digital microphone mode for left ADC and right ADC. Treat data on DIN as digital microphone data
{0x52, 0x00}, // 36. Unmute left ADC and right ADC
{0x41, 0x00}, // 37. Set the left DAC digital volume control to 0 dB
{0x42, 0x00}, // 38. Set the right DAC digital volume control to 0 dB
{0x3f, 0xd6}, // 39. Power up left and right DAC channel, routing left and right audio interface
{0x40, 0x00} // 40. Unmute the DAC digital volume control

Anyway there is no output at Dac HPL and HPR. Using oscilloscope I see the PDM data and PDM clock is ok.

B.R.

Y.W. Fan

Y.W. Fan,

When using digital mic input you need to connect DIN and DOUT pins (externally) so the output from ADC (DOUT) is fed to the DAC input (DIN).
Loopback should be disabled.
This is also mentioned at the end of the post you've linked at your original post.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Thanks for your reply. 

There is still some setting concept confuse me.

I am new to this codec.

Originally, I thought digital mic data will be process then send to DAC.

So what you mean is that when using digital microphone,

If we set the output clock pin to MISO and input data pin to MFP3, the hardware will processing PDM data then output I2S data at DOUT pin. (Will not route directly to DAC)

On the other hand, I found in datasheet we could set DIN as digital microphone input. If we set  the output clock pin to MISO and input data pin to DIN, does this mean the connection of DIN and DOUT will be unnecessary? (it will route directly to DAC?)

B.R.

Y.W. Fan

Hi, Ivan

In my application, I don't want BCLK and WCLK as master (Don't want any signal coming out). So I set BCLK and WCLK as input.

Then I try your suggest. Connect din and dout or/and set 0x1D bit D4 to 1.

There is no signal coming out from DOUT.

BCLK and WCLK as master is a must?

Following is my setting:

{0x00, 0x00}, // 0. Initialize to page 0
{0x01, 0x01}, // 1. Initialize the device through software reset
{0x04, 0x03}, // 2. Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK
{0x05, 0x93}, // 3. Power up PLL, set PLL divider P=1 and PLL divider R=3
{0x06, 0x07}, // 4. Set PLL divider J=7
{0x07, 0x00}, // 5. Set PLL divider D=0000
{0x08, 0x00}, // 6.

{0x0b, 0x83}, // 7. Power up and set NDAC divider = 3
{0x0c, 0x87}, // 8. Power up and set MDAC divider = 7
{0x0d, 0x01}, // 9. Set DOSR = 256 MSB //for 16Khz
{0x0e, 0x00}, //10. Set DOSR = 256 LSB //for 16Khz
{0x1b,0x00},  //11. Set BCLK and MCLK as input.
{0x3c, 0x08}, //12. DAC mode to PRB_P4

{0x12, 0x83}, // 13. Power up and set NADC divider = 3
{0x13, 0x8E}, // 14. Power up and set MADC divider = 14
{0x14, 0x80}, // 15. Set AOSR = 128 //for16Khz
{0x37, 0x0E}, // 16. MISO/MFP4 Function Control Register set to DMIC_CLK

//turn off BDIV_CLKIN
//{0x1d, 0x05}, //13. BDIV_CLKIN = DAC_MOD_CLK
//{0x1e, 0x82}, //14. Power up and set BCLK N divider = 2

{0x51, 0xdc}, // 17. Power up left ADC and right ADC. Enable digital microphone mode for left ADC and right ADC. Treat data on SCLK as digital microphone data
// should be 0x50??

{0x52, 0x00}, // 18. Unmute left ADC and right ADC

{0x00, 0x01}, //15. Select page 1
{0x01, 0x08}, //16. Disable internal crude AVdd in presence of external AVdd supply
{0x02, 0x00}, //17. Enable master analog power control
{0x7b, 0x01}, //18. Set the REF charging time to 40ms
{0x0a, 0x00}, //19. Set the input common mode to 0.9V and output common mode for headphone to input common mode

{0x0c, 0x08}, //20. Route left DAC & INL to HPL
{0x0d, 0x08}, //21. Route right DAC & INR to HPR
{0x03, 0x00}, //22. Set the DAC PTM mode to PTM_P3
{0x04, 0x00}, //23.

{0x10, 0x00}, //24. Set the HPL gain to -4dB ********** // 目前改成0dB
{0x11, 0x00}, //25. Set the HPR gain to -4dB **********
{0x14, 0x29}, //26. HP soft stepping settings for optimal pop performance at power up. Rpop used is 6k with N = 6 & soft step = 20usec
{0x09, 0x30}, //27. Power up HPL and HPR drivers
//#----------- Wait for 2.5 sec for soft stepping to take effect
//#----------- else read page 1, register 63d, D(7:6). When = “11” soft-stepping is complete
{0x00, 0x00}, //28. Select page 0
{0x44, 0x00}, //29. DRC Control Register 1 , disable DRC
{0x3f, 0xd6}, //30. Power up the left and right DAC channels and route the left channel I2S data to left channel DAC and right channel I2S data to right channel DAC
{0x40, 0x00} //31. Unmute the DAC digital volume control

Thx.

B.R.

Y.W. Fan

Y.W. Fan,

BCLK and WCLK as master is not a must.
The GUI of TLV320DAC3203 includes a script for Digital Mic loopback:
###############################################
# Digital Microphone Script Loopback
# ---------------------------------------------
# Digital microphone data (DOUT) is sent to
# the DAC's DIN pin internally. DOUT data
# is also sent to the USB controller.
###############################################



###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# NADC = 2, MADC = 16, dividers powered on
w 30 12 82 90
#
# AOSR = 64
w 30 14 40
#
# Digital Loopback
# Routes DOUT to DIN internally, DOUT pin
# is still output, DIN pin is ignored
w 30 1D 10
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P2 and PRB_R2 selected
w 30 3C 02 02
#
################################################
# High-pass first order Butterworth2 filter,
# fc = 80 Hz
###############################################
#
# Write to Buffer A:
#
# BIQUAD A, Left Channel (Page 8, Register 36, C7-C11)
w 30 00 08
w 30 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# BIQUAD A, Right Channel (Page 9, Register 44, C39-C43)
w 30 00 09
w 30 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# Write to Buffer B:
#
# BIQUAD A, Left Channel (Page 26, Register 36, C7-C11)
w 30 00 1A
w 30 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# BIQUAD A, Right Channel (Page 27, Register 44, C39-C43)
w 30 00 1B
w 30 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
###############################################




###############################################
# Configure ADC Channel
###############################################
#
# Select Page 0
w 30 00 00
#
# Configure MISO as clock output for DIGMIC
w 30 37 0E
#
# LADC and RADC enabled for DIGMIC
# Route SCLK as DIGMIC_DATA
# Power up LADC/RADC
w 30 51 DC
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################



###############################################
# Configure DAC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop: 5 time constants, 6k resistance
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Select Page 1
w 30 00 01
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Power up HPL/HPR
w 30 09 30
#
# Select Page 0
w 30 00 00
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

You could try this, however I think there is not so much difference between.
I'll keep looking for a root cause for not getting output signal.
What are your sampling frequencies? I ask this to verify the clock settings.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi, Ivan

Thx for your patience.

So by setting BCLK and MCLK as master or slave are no difference, I got it. I will keep looking for bug.

My sample frequency is 16kHz. And in my application, I input 4M to MCLK pin.

When I use I2S this codec work fine.

But if I change to PDM, (I set MISO output 2MHz), there is no signal coming out at DOUT. The Dmic(PDM) work fine I sure.

Thanks for your info, I will compare this to my code setting.

B.R.

Y.W. Fan

Hi, Ivan

There is another issue.

In I2S, I found the group delay (filter A in 16k 32 bits) is more than the value in data sheet.

My measurement get 2.2ms. But from datasheet (page 42, 21/Fs), it should be 1.3ms.

But I am sure I set the PRB in filter A class. Do you have any idea about what possible reason or cause could be for this case?

B.R.

Y.W. Fan