Other Parts Discussed in Thread: DIX4192, , SRC4382
It is not clear to me how PLL2, which is part of the DIR in the SRC4392 as well as the SRC4382 and the DIX4192, operates. The data sheet states that there are 3 different frequencies available from the PLL2, namely 128x fs, 256x fs and 512x fs. However, there are no register bits to select between them. There is a post-divider to divide down the output of PLL2, but is has 4 possible settings, so this appears to be distinct from the PLL2 operation. My own experiments indicate that the device selects automatically between the three PLL2 modes depending on the sampling frequency of the incoming signal.
There are read-only bits in receiver status register 1, which allegedly indicate the "maximum available RXCKO rate". I suspect they actually indicate the PLL2 mode that has been selected automatically.
If this is true, it means that there must be two boundary frequencies of the incoming signal at which the PLL2 switches its mode. There is no mentioning of this in the data sheet at all, even though it would be interesting to know where those switchover frequencies are, or which frequency ranges are guaranteed to be free of such automatic switching.
Am I describing the situation correctly? Or is there something I have overlooked? What can be said about the switchover frequencies of PLL2?
