RTOS/PROCESSOR-SDK-AM335X: Starter Kit audio codec example

/*
 * Aic31.c
 *
 * APIs to configure the AIC31 codec.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

#include "Codecif.h"
#include "Aic31.h"

/******************************************************************************
**                      INTERNAL MACRO DEFINITIONS
*******************************************************************************/
//#define HD_DETECT

/*
** Register Address for AIC31 Codec
*/
#define AIC31_P0_REG0               (0)  /* Page Select  */
#define AIC31_P0_REG1               (1)  /* Software Reset */
#define AIC31_P0_REG2               (2)  /* Codec Sample Rate Select */
#define AIC31_P0_REG3               (3)  /* PLL Programming A */
#define AIC31_P0_REG4               (4)  /* PLL Programming B */
#define AIC31_P0_REG5               (5)  /* PLL Programming C */
#define AIC31_P0_REG6               (6)  /* PLL Programming D */
#define AIC31_P0_REG7               (7)  /* Codec Datapath Setup */
#define AIC31_P0_REG8               (8)  /* Audio Serial Data I/f Control A */
#define AIC31_P0_REG9               (9)  /* Audio Serial Data I/f Control B */
#define AIC31_P0_REG10              (10) /* Audio Serial Data I/f Control C */
#define AIC31_P0_REG11              (11) /* Audio Codec Overflow Flag */
#define AIC31_P0_REG12              (12) /* Audio Codec Digital Filter Ctrl */
#define AIC31_P0_REG13              (13) /* Headset / Button Press Detect A */
#define AIC31_P0_REG14              (14) /* Headset / Button Press Detect B */
#define AIC31_P0_REG15              (15) /* Left ADC PGA Gain Control */
#define AIC31_P0_REG16              (16) /* Right ADC PGA Gain Control */
#define AIC31_P0_REG17              (17) /* MIC3L/R to Left ADC Control */
#define AIC31_P0_REG18              (18) /* MIC3L/R to Right ADC Control */
#define AIC31_P0_REG19              (19) /* LINE1L to Left ADC Control */
#define AIC31_P0_REG20              (20) /* LINE2L to Left ADC Control */
#define AIC31_P0_REG21              (21) /* LINE1R to Left ADC Control */
#define AIC31_P0_REG22              (22) /* LINE1R to Right ADC Control */
#define AIC31_P0_REG23              (23) /* LINE2R to Right ADC Control */
#define AIC31_P0_REG24              (24) /* LINE1L to Right ADC Control */
#define AIC31_P0_REG25              (25) /* MICBIAS Control */
#define AIC31_P0_REG26              (26) /* Left AGC Control A */
#define AIC31_P0_REG27              (27) /* Left AGC Control B */
#define AIC31_P0_REG28              (28) /* Left AGC Control C */
#define AIC31_P0_REG29              (29) /* Right AGC Control A */
#define AIC31_P0_REG30              (30) /* Right AGC Control B */
#define AIC31_P0_REG31              (31) /* Right AGC Control C */
#define AIC31_P0_REG32              (32) /* Left AGC Gain */
#define AIC31_P0_REG33              (33) /* Right AGC Gain */
#define AIC31_P0_REG34              (34) /* Left AGC Noise Gate Debounce */
#define AIC31_P0_REG35              (35) /* Right AGC Noise Gate Debounce */
#define AIC31_P0_REG36              (36) /* ADC Flag */
#define AIC31_P0_REG37              (37) /* DAC Power and Output Driver Control */
#define AIC31_P0_REG38              (38) /* High Power Output Driver Control*/
#define AIC31_P0_REG40              (40) /* High Power Output Stage Control*/
#define AIC31_P0_REG41              (41) /* DAC Output Switching Control */
#define AIC31_P0_REG42              (42) /* Output Driver Pop Reduction */
#define AIC31_P0_REG43              (43) /* Left DAC Digital Volume Control */
#define AIC31_P0_REG44              (44) /* Right DAC Digital Volume Control */
#define AIC31_P0_REG45              (45) /* LINE2L to HPLOUT Volume Control */
#define AIC31_P0_REG46              (46) /* PGA_L to HPLOUT Volume Control */
#define AIC31_P0_REG47              (47) /* DAC_L1 to HPLOUT Volume Control */
#define AIC31_P0_REG48              (48) /* LINE2R to HPLOUT Volume Control */
#define AIC31_P0_REG49              (49) /* PGA_R to HPLOUT Volume Control */
#define AIC31_P0_REG50              (50) /* DAC_R1 to HPLOUT Volume Control */
#define AIC31_P0_REG51              (51) /* HPLOUT Output Level Control */
#define AIC31_P0_REG52              (52) /* LINE2L to HPLCOM Volume Control */
#define AIC31_P0_REG53              (53) /* PGA_L to HPLCOM Volume Control */
#define AIC31_P0_REG54              (54) /* DAC_L1 to HPLCOM Volume Control */
#define AIC31_P0_REG55              (55) /* LINE2R to HPLCOM Volume Control */
#define AIC31_P0_REG56              (56) /* PGA_R to HPLCOM Volume Control */
#define AIC31_P0_REG57              (57) /* DAC_R1 to HPLCOM Volume Control */
#define AIC31_P0_REG58              (58) /* HPLCOM Output Level Control */
#define AIC31_P0_REG59              (59) /* LINE2L to HPROUT Volume Control */
#define AIC31_P0_REG60              (60) /* PGA_L to HPROUT Volume Control */
#define AIC31_P0_REG61              (61) /* DAC_L1 to HPROUT Volume Control */
#define AIC31_P0_REG62              (62) /* LINE2R to HPROUT Volume Control */
#define AIC31_P0_REG63              (63) /* PGA_R to HPROUT Volume Control  */
#define AIC31_P0_REG64              (64) /* DAC_R1 to HPROUT Volume Control */
#define AIC31_P0_REG65              (65) /* HPROUT Output Level Control */
#define AIC31_P0_REG66              (66) /* LINE2L to HPRCOM Volume Control  */
#define AIC31_P0_REG67              (67) /* PGA_L to HPRCOM Volume Control */
#define AIC31_P0_REG68              (68) /* DAC_L1 to HPRCOM Volume Control */
#define AIC31_P0_REG69              (69) /* LINE2R to HPRCOM Volume Control */
#define AIC31_P0_REG70              (70) /* PGA_R to HPRCOM Volume Control */
#define AIC31_P0_REG71              (71) /* DAC_R1 to HPRCOM Volume Control */
#define AIC31_P0_REG72              (72) /* HPRCOM Output Level Control */
#define AIC31_P0_REG73              (73) /* LINE2L to MONO_LOP/M Volume Control*/
#define AIC31_P0_REG74              (74) /* PGA_L to MONO_LOP/M Volume Control */
#define AIC31_P0_REG75              (75) /* DAC_L1 to MONO_LOP/M Volume Control */
#define AIC31_P0_REG76              (76) /* LINE2R to MONO_LOP/M Volume Control */
#define AIC31_P0_REG77              (77) /* PGA_R to MONO_LOP/M Volume Control */
#define AIC31_P0_REG78              (78) /* DAC_R1 to MONO_LOP/M Volume Control */
#define AIC31_P0_REG79              (79) /* MONO_LOP/M Output Level Control */
#define AIC31_P0_REG80              (80) /* LINE2L to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG81              (81) /* PGA_L to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG82              (82) /* DAC_L1 to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG83              (83) /* LINE2R to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG84              (84) /* PGA_R to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG85              (85) /* DAC_R1 to LEFT_LOP/M Volume Control */
#define AIC31_P0_REG86              (86) /* LEFT_LOP/M Output Level Control */
#define AIC31_P0_REG87              (87) /* LINE2L to RIGHT_LOP/M Volume Control */
#define AIC31_P0_REG88              (88) /* PGA_L to RIGHT_LOP/M Volume Control */
#define AIC31_P0_REG89              (89) /* DAC_L1 to RIGHT_LOP/M Volume Control */
#define AIC31_P0_REG90              (90) /* LINE2R to RIGHT_LOP/M Volume Control */
#define AIC31_P0_REG91              (91) /* PGA_R to RIGHT_LOP/M Volume Control */
#define AIC31_P0_REG92              (92) /* DAC_R1 to RIGHT_LOP/M Volume Control*/
#define AIC31_P0_REG93              (93) /* RIGHT_LOP/M Output Level Control */
#define AIC31_P0_REG94              (94) /* Module Power Status */
#define AIC31_P0_REG95              (95) /**< O/P Driver Short Circuit Detection Status*/
#define AIC31_P0_REG96              (96) /* Sticky Interrupt Flags */
#define AIC31_P0_REG97              (97) /* Real-time Interrupt Flags  */
#define AIC31_P0_REG98              (98) /* GPIO1 Control */
#define AIC31_P0_REG99              (99) /* GPIO2 Control */
#define AIC31_P0_REG100             (100)  /* Additional GPIO Control A */
#define AIC31_P0_REG101             (101)  /* Additional GPIO Control B */
#define AIC31_P0_REG102             (102)  /* Clock Generation Control */

#define AIC31_RESET                 (0x80)

#define AIC31_SLOT_WIDTH_16         (0u << 4u)
#define AIC31_SLOT_WIDTH_20         (1u << 4u)
#define AIC31_SLOT_WIDTH_24         (2u << 4u)
#define AIC31_SLOT_WIDTH_32         (3u << 4u)

/******************************************************************************
**                          FUNCTION DEFINITIONS
*******************************************************************************/

void AIC3120_Config(unsigned int baseAddr)
{
      unsigned char u8DataVar=0;
//     /* Select Page 0 */
//    CodecRegWrite(baseAddr, AIC31_P0_REG0, 0);  
//  
//    /* Reset the codec */
//    CodecRegWrite(baseAddr, AIC31_P0_REG1, 1);
    
    //PLL_clkin = BCLK,codec_clkin = PLL_CLK
    //w 30 04 07
    //> 92
    //> 10
    //> 00
    //> 00
    u8DataVar = CodecRegRead(baseAddr, AIC31_P0_REG4);
    CodecRegWrite(baseAddr, AIC31_P0_REG4, 0x07);  
    u8DataVar = CodecRegRead(baseAddr, AIC31_P0_REG4);
    
    CodecRegWrite(baseAddr, AIC31_P0_REG5, 0x92); 
    CodecRegWrite(baseAddr, AIC31_P0_REG6, 0x10); 
    CodecRegWrite(baseAddr, AIC31_P0_REG7, 0x00); 
    CodecRegWrite(baseAddr, AIC31_P0_REG8, 0x00); 
    
    //mode is i2s,wordlength is 16
    //w 30 1b 00
    CodecRegWrite(baseAddr, AIC31_P0_REG27, 0x00); 
    
    //NDAC is powered up and set to 4
    //MDAC is powered up and set to 4
    //w 30 0b 82
    //w 30 0C 88
    CodecRegWrite(baseAddr, 0x0B, 0x82);
    CodecRegWrite(baseAddr, 0x0C, 0x82);
    
    //w 30 12 88
    //82
    //DOSR = 128, DOSR(9:8) = 0
    //80
    //DOSR(7:0) = 128
    //80
    CodecRegWrite(baseAddr, 0x12, 0x88);
    CodecRegWrite(baseAddr, 0x13, 0x82);
    CodecRegWrite(baseAddr, 0x14, 0x80);
    CodecRegWrite(baseAddr, 0x15, 0x80);
    
    //DAC => volume control thru pin disable 
    //w 30 74 00
    CodecRegWrite(baseAddr, 0x74, 0x00);
    
    //DAC => drc disable, th and hy
    //w 30 44 00
    CodecRegWrite(baseAddr, 0x44, 0x00);
    
    //DAC => 0 db gain left
    //w 30 41 00
    //DAC => 0 db gain right
    //00
    CodecRegWrite(baseAddr, 0x41, 0x00);
    CodecRegWrite(baseAddr, 0x42, 0x00);
    
    //page 3 (touch screen) is selected
    //SAR configuration
    //w 30 00 03
    //w 30 02 18
    //w 30 06 80
    //w 30 03 01
    //w 30 11 00
    //w 30 13 10
    //w 30 03 25
    CodecRegWrite(baseAddr, 0x00, 0x03);
    CodecRegWrite(baseAddr, 0x02, 0x18);
    CodecRegWrite(baseAddr, 0x06, 0x80);
    CodecRegWrite(baseAddr, 0x03, 0x01);
    CodecRegWrite(baseAddr, 0x11, 0x00);
    CodecRegWrite(baseAddr, 0x13, 0x10);
    CodecRegWrite(baseAddr, 0x03, 0x25);
    
    
    //page 1 is selected
    //w 30 00 01
    //De-pop, Power on = 800 ms, Step time = 4 ms
    //w 30 21 4e
    CodecRegWrite(baseAddr, 0x00, 0x01);
    CodecRegWrite(baseAddr, 0x21, 0x4E);
    
    //HPL and HPR powered up
    //w 30 1f c2
    CodecRegWrite(baseAddr, 0x1F, 0xC2);
    
    //LDAC routed to HPL, RDAC routed to HPR
    //w 30 23 88
    CodecRegWrite(baseAddr, 0x23, 0x88);
    
    //HPL unmute and gain 1db
    //w 30 28 0e
    //HPR unmute and gain 1db
    //0e
    CodecRegWrite(baseAddr, 0x28, 0x0E);
    CodecRegWrite(baseAddr, 0x29, 0x0E);
    
    //No attenuation on HP
    //w 30 24 00
    //w 30 25 00
    CodecRegWrite(baseAddr, 0x24, 0x00);
    CodecRegWrite(baseAddr, 0x25, 0x00);
    
    //MIC BIAS = AVDD
    //w 30 2e 0b
    CodecRegWrite(baseAddr, 0x2E, 0x0B);
    
    //MICPGA P = MIC 10k
    //w 30 30 40
    //MICPGA M - CM 10k
    //40
    CodecRegWrite(baseAddr, 0x30, 0x40);
    CodecRegWrite(baseAddr, 0x31, 0x40);
    
    //page 0 is selected
    //w 30 00 00
    CodecRegWrite(baseAddr, 0x00, 0x00);
    
    //select DAC DSP mode 11 & enable adaptive filter
    //w 30 3c 0b
    //w 30 00 08
    //w 30 01 04
    //w 30 00 00
    CodecRegWrite(baseAddr, 0x3C, 0x0B);
    
    //page 8 is selected
    CodecRegWrite(baseAddr, 0x00, 0x08);
    CodecRegWrite(baseAddr, 0x01, 0x04);
    
    //page 0 is selected
    CodecRegWrite(baseAddr, 0x00, 0x00);
    
    //POWERUP DAC left and right channels (soft step disable)
    //w 30 3f d6
    //UNMUTE DAC left and right channels
    //00
    CodecRegWrite(baseAddr, 0x3F, 0xD6);
    CodecRegWrite(baseAddr, 0x40, 0x00);
    
    //POWERUP ADC channel
    //w 30 51 80
    //UNMUTE ADC channel
    //00
    CodecRegWrite(baseAddr, 0x51, 0x80);
    CodecRegWrite(baseAddr, 0x52, 0x00);
    
    //page 1 is selected
    //w 30 00 01
    CodecRegWrite(baseAddr, 0x00, 0x01);
       
    //w 30 23 08
    //w 30 23 00
    //w 30 26 00
    //w 30 27 00
    //w 30 23 40
    //w 30 23 44
    //w 30 26 b0
    //w 30 27 b0
    //w 30 2a 0d
    //w 30 2b 0d
    CodecRegWrite(baseAddr, 0x23, 0x08);
    CodecRegWrite(baseAddr, 0x23, 0x00);
    CodecRegWrite(baseAddr, 0x26, 0x00);
    CodecRegWrite(baseAddr, 0x27, 0x00);
    CodecRegWrite(baseAddr, 0x23, 0x40);
    CodecRegWrite(baseAddr, 0x23, 0x44);
    CodecRegWrite(baseAddr, 0x26, 0xB0);
    CodecRegWrite(baseAddr, 0x27, 0xB0);
    CodecRegWrite(baseAddr, 0x2A, 0x0D);
    CodecRegWrite(baseAddr, 0x2B, 0x0D);
    
    //w 30 00 01
    //Unmute Class-D Left
    //w 30 2a 1c
    //Unmute Class-D Right
    //w 30 2b 1c
    CodecRegWrite(baseAddr, 0x00, 0x01);
    CodecRegWrite(baseAddr, 0x2A, 0x1C);
    CodecRegWrite(baseAddr, 0x2B, 0x1C);
    
    //Power-up Class-D drivers
    //w 30 20 c6
    //w 30 24 30
    //w 30 25 30
    //w 30 31 00
    CodecRegWrite(baseAddr, 0x20, 0xC6);
    CodecRegWrite(baseAddr, 0x24, 0x30);
    CodecRegWrite(baseAddr, 0x25, 0x30);
    CodecRegWrite(baseAddr, 0x31, 0x00);
  
}

/**
 * \brief   Resets the AIC31 Codec
 *
 * \param   baseAddr     Base Address of the interface connected to AIC31
 *
 * \return  None.
 *
 **/
void AIC31Reset(unsigned int baseAddr)
{
    /* Select Page 0 */
    CodecRegWrite(baseAddr, AIC31_P0_REG0, 0);

    /* Reset the codec */
    CodecRegWrite(baseAddr, AIC31_P0_REG1, AIC31_RESET);
}

/**
 * \brief   Configures the data format and slot width
 *
 * \param   baseAddr     Base Address of the interface connected to AIC31
 * \param   dataType     Data type for the codec operation
 * \param   slotWidth    Slot width in bits
 * \param   dataOff      The number of clocks from the word clock rising edge
 *                       to capture the actual data
 *            dataType can take the values \n
 *               AIC31_DATATYPE_I2S - for I2S mode \n
 *               AIC31_DATATYPE_DSP - for DSP mode \n
 *               AIC31_DATATYPE_RIGHTJ - for right aligned data \n
 *               AIC31_DATATYPE_LEFTJ - for left aligned data \n
 *
 * \return  None.
 *
 **/
void AIC31DataConfig(unsigned int baseAddr, unsigned char dataType,
                     unsigned char slotWidth, unsigned char dataOff)
{
    unsigned char slot;

    switch(slotWidth)
    {
        case 16:
            slot = AIC31_SLOT_WIDTH_16;
        break;

        case 20:
            slot = AIC31_SLOT_WIDTH_20;
        break;

        case 24:
            slot = AIC31_SLOT_WIDTH_24;
        break;

        case 32:
            slot = AIC31_SLOT_WIDTH_32;
        break;

        default:
            slot = AIC31_SLOT_WIDTH_16;
        break;
    }


    /* Write the data type and  slot width */
    CodecRegWrite(baseAddr, AIC31_P0_REG9, (dataType | slot));

    /* valid data after dataOff number of clock cycles */
    CodecRegWrite(baseAddr, AIC31_P0_REG10, dataOff);
}

/**
 * \brief   Configures the data format and slot width
 *
 * \param   baseAddr     Base Address of the interface connected to AIC31
 * \param   mode         section of the codec (ADC/DAC) for which the sample
 *                       rate needs to be configured
 * \param   sampleRate   Sample rate in samples per second
 *              mode can take the values \n
 *                AIC31_MODE_ADC - for selecting ADC \n
 *                AIC31_MODE_DAC - for selecting DAC \n
 *                AIC31_MODE_BOTH - for both ADC and DAC \n
 *              sampleRate can be \n
 *                 8000, 11025, 16000, 22050, 24000, 32000, 44100,
 *                 48000 or  96000. \n
 *          The fs is derived from the equation
 *                fs = (PLL_IN * [pllJval.pllDval] * pllRval) /(2048 * pllPval).
 *          So the values are set for PLL_IN = 24000 kHz
 *
 * \return  None.
 *
 **/
void AIC31SampleRateConfig(unsigned int baseAddr, unsigned int mode,
                           unsigned int sampleRate)
{
    unsigned char fs;
    unsigned char ref = 0x0Au;
    unsigned char temp;
    unsigned char pllPval = 2u; //1u; for 12000 kHz
    unsigned char pllRval = 1u;
    unsigned char pllJval = 8u;
    unsigned short pllDval = 1920u;

    /* Select the configuration for the given sampling rate */
    switch(sampleRate)
    {
        case 8000:
            fs = 0xAAu;
        break;

        case 11025:
            fs = 0x66u;
            ref = 0x8Au;
            pllJval = 7u;
            pllDval = 5264u;
        break;

        case 16000:
            fs = 0x44u;
        break;

        case 22050:
            fs = 0x22u;
            ref = 0x8Au;
            pllJval = 7u;
            pllDval = 5264u;
        break;

        case 24000:
            fs = 0x22u;
        break;

        case 32000:
            fs = 0x11u;
        break;

        case 44100:
            ref = 0x8Au;
            fs = 0x00u;
            pllJval = 7u;
            pllDval = 5264u;
        break;

        case 48000:
            fs = 0x00u;
        break;

        case 96000:
            ref = 0x6Au;
            fs = 0x00u;
        break;

        default:
            fs = 0x00u;
        break;
    }

    temp = (mode & fs);

    /* Set the sample Rate */
    CodecRegWrite(baseAddr, AIC31_P0_REG2, temp);

    CodecRegWrite(baseAddr, AIC31_P0_REG3, 0x80 | pllPval);

    /* use PLL_CLK_IN as MCLK */
    CodecRegWrite(baseAddr, AIC31_P0_REG102, 0x08);

    /* Use PLL DIV OUT as codec CLK IN */
    CodecRegBitClr(baseAddr, AIC31_P0_REG101, 0x01);

    /* Select GPIO to output the divided PLL IN */
    CodecRegWrite(baseAddr, AIC31_P0_REG98, 0x20);

    CodecRegWrite(baseAddr, AIC31_P0_REG4, pllJval << 2);

    /* Configure the PLL divide registers */
    CodecRegWrite(baseAddr, AIC31_P0_REG5, (pllDval >> 6) & 0xFF);
    CodecRegWrite(baseAddr, AIC31_P0_REG6, (pllDval & 0x3F) << 2);

    CodecRegWrite(baseAddr, AIC31_P0_REG11, pllRval);

    /* Enable the codec to be master for fs and bclk */
    CodecRegWrite(baseAddr, AIC31_P0_REG8, 0xD0);

    CodecRegWrite(baseAddr, AIC31_P0_REG7, ref);
}

/**
 * \brief   Initializes the ADC section of the AIC31 Codec
 *
 * \param   baseAddr     Base Address of the interface connected to AIC31
 *
 * \return  None.
 *
 **/
void AIC31ADCInit(unsigned int baseAddr)
{
    /* enable the programmable PGA for left and right ADC  */
    CodecRegWrite(baseAddr, AIC31_P0_REG15, 0x00);
    CodecRegWrite(baseAddr, AIC31_P0_REG16, 0x00);

    /* MIC3L/R is not connected to the left ADC PGA */
    CodecRegWrite(baseAddr, AIC31_P0_REG17, 0xFF);

    /* MIC3L/R is not connected to the right ADC PGA */
    CodecRegWrite(baseAddr, AIC31_P0_REG18, 0xFF);

    /* power on the Line L1R */
    CodecRegWrite(baseAddr, AIC31_P0_REG19, 0x04);

    /* power on the Line LIL */
    CodecRegWrite(baseAddr, AIC31_P0_REG22, 0x04);
}

/**
 * \brief   Initializes the DAC section of the AIC31 Codec
 *
 * \param   baseAddr     Base Address of the interface connected to AIC31
 *
 * \return  None.
 *
 **/
void AIC31DACInit(unsigned int baseAddr)
{
    /* power up the left and right DACs */
    CodecRegWrite(baseAddr, AIC31_P0_REG37, 0xE0);

    /* select the DAC L1 R1 Paths */
    CodecRegWrite(baseAddr, AIC31_P0_REG41, 0x02);
    CodecRegWrite(baseAddr, AIC31_P0_REG42, 0x6C);


    /* DAC L to HPLOUT Is connected */
    CodecRegWrite(baseAddr, AIC31_P0_REG47, 0x80);
    CodecRegWrite(baseAddr, AIC31_P0_REG51, 0x09);

    /* DAC R to HPROUT is connected */
    CodecRegWrite(baseAddr, AIC31_P0_REG64, 0x80);
    CodecRegWrite(baseAddr, AIC31_P0_REG65, 0x09);

    /* DACL1 connected to LINE1 LOUT */
    CodecRegWrite(baseAddr, AIC31_P0_REG82, 0x80);
    CodecRegWrite(baseAddr, AIC31_P0_REG86, 0x09);

    /* DACR1 connected to LINE1 ROUT */
    CodecRegWrite(baseAddr, AIC31_P0_REG92, 0x80);
    CodecRegWrite(baseAddr, AIC31_P0_REG93, 0x09);

    /* unmute the DAC */
    CodecRegWrite(baseAddr, AIC31_P0_REG43, 0x00);
    CodecRegWrite(baseAddr, AIC31_P0_REG44, 0x00);

#ifdef HD_DETECT
    unsigned char aic_reg13=0, aic_reg14=0;
    unsigned int i=0;
    aic_reg13 = CodecRegRead(baseAddr, AIC31_P0_REG13);
    aic_reg14 = CodecRegRead(baseAddr, AIC31_P0_REG14);

    aic_reg13 |= 0x80;
    CodecRegWrite(baseAddr, AIC31_P0_REG13, aic_reg13);

    for (i=0;i<1000;i++);

while(1)
{
    aic_reg13 = CodecRegRead(baseAddr, AIC31_P0_REG13);
    aic_reg14 = CodecRegRead(baseAddr, AIC31_P0_REG14);
    for (i=0;i<1000;i++);

}
#endif
}

/***************************** End Of File ***********************************/

/**
 * \file   mcasp.c
 *
 * \brief  This file contains functions which configure McASP pins
 */

/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*/
/*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

#include "soc_AM335x.h"
#include "hw_control_AM335x.h"
#include "hw_types.h"
#include "evmskAM335x.h"
#include "hw_cm_per.h"

#define MCASP_SEL_MODE            0x04
#define MCASP_0_SEL_MODE          0x00
#define CLKOUT1_SEL_MODE          0x03

/**
 * \brief   This function selects the McASP instance 1 pins
 *          
 * \param   None
 *
 * \return  TRUE/FALSE.
 *
 * \note    This muxing depends on the profile in which the EVM is configured.
 */
void McASP1PinMuxSetup(void)
{
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = 
                  CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE 
                  | MCASP_SEL_MODE;            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) = 
                  CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                  | MCASP_SEL_MODE;            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
                  CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                  | MCASP_SEL_MODE;            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) = 
                  CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE 
                  | MCASP_SEL_MODE;   
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_XDMA_EVENT_INTR(0)) = 
                  CLKOUT1_SEL_MODE;
}


////////////////////////////////ADDED BY GAURAV/////////////////////////////////////////
/**
 * \brief   This function selects the McASP instance 0 pins
 *          
 * \param   None
 *
 * \return  TRUE/FALSE.
 *
 * \note    This muxing depends on the profile in which the EVM is configured.
 */
void McASP0PinMuxSetup(void)
{

            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AXR1) = 
                          CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE 
                          | MCASP_0_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_ACLKX) = 
                          CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE
                          | MCASP_0_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_FSX) =
                          CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE
                          | MCASP_0_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AXR0) = 
                          CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE 
                          | MCASP_0_SEL_MODE;    
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKX) = 
                          CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE 
                          | MCASP_0_SEL_MODE;    
}

/**
 * \brief   This function enables McASP 1 clocks
 *          
 * \param   None
 *
 * \return  None.
 *
 */
void McASP1ModuleClkConfig(void)
{
    HWREG(SOC_PRCM_REGS + CM_PER_MCASP1_CLKCTRL) =
                             CM_PER_MCASP1_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_PRCM_REGS + CM_PER_MCASP1_CLKCTRL) &
      CM_PER_MCASP1_CLKCTRL_MODULEMODE) != CM_PER_MCASP1_CLKCTRL_MODULEMODE_ENABLE);


    /*
    ** Waiting for IDLEST field in CM_PER_MCASP1_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_MCASP1_CLKCTRL_IDLEST_FUNC <<
           CM_PER_MCASP1_CLKCTRL_IDLEST_SHIFT)!=
          (HWREG(SOC_CM_PER_REGS + CM_PER_MCASP1_CLKCTRL) &
           CM_PER_MCASP1_CLKCTRL_IDLEST));

}


/**
 * \brief   This function enables McASP 0 clocks
 *          
 * \param   None
 *
 * \return  None.
 *
 */
void McASP0ModuleClkConfig(void)
{
    HWREG(SOC_PRCM_REGS + CM_PER_MCASP0_CLKCTRL) =
                             CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_PRCM_REGS + CM_PER_MCASP0_CLKCTRL) &
      CM_PER_MCASP0_CLKCTRL_MODULEMODE) != CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE);


    /*
    ** Waiting for IDLEST field in CM_PER_MCASP1_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_MCASP0_CLKCTRL_IDLEST_FUNC <<
           CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT)!=
          (HWREG(SOC_CM_PER_REGS + CM_PER_MCASP0_CLKCTRL) &
           CM_PER_MCASP0_CLKCTRL_IDLEST));

}

/****************************** End Of File *********************************/

/*
 * ToneLoop.c
 *
 * Functions for looping a tone infinitely.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

#include "edma_event.h"
#include "interrupt.h"
//#include "evmAM335x.h"
#include "evmskAM335x.h"
#include <am335x_bsp\am335x_include\mcasp.h>
#include "soc_AM335x.h"
#include <am335x_bsp\am335x_include\edma.h>
#include <am335x_bsp\am335x_include\hsi2c.h>
#include "tx_api.h"
#include <string.h>
#include "Aic31.h"
#include "Codecif.h"
#include "toneRaw.h"
#include "Cfg.h"
//#include "i2cApi.h"

/******************************************************************************
**                      INTERNAL MACRO DEFINITIONS
******************************************************************************/
#ifdef EVMSK_ALPHA
  #define SOC_I2C_REGS      SOC_I2C_1_REGS
  #define SYS_INT_I2CINT    SYS_INT_I2C1INT
#else
  #define SOC_I2C_REGS      SOC_I2C_0_REGS
  #define SYS_INT_I2CINT    SYS_INT_I2C0INT
#endif

#define I2S_SLOTS_L_R                 (0x03u)

/* Definitions for sample tone */
#define TONE_START_ADDR               ((unsigned int)toneRaw)
#define TONE_NUM_BYTES                (sizeof(toneRaw))
#define TONE_END_ADDR                 (TONE_START_ADDR + TONE_NUM_BYTES - 1)
#define PARAM1_NUM_SAMPLES_L          ((unsigned int)(TONE_NUM_BYTES  \
                                       / (TONE_WORD_SIZE >> 3)))
#define PARAM1_BCNT                   (65000)
#define PARAM1_CCNT                   ((unsigned int) \
                                       (PARAM1_NUM_SAMPLES_L / PARAM1_BCNT))
#define PARAM2_START_ADDR             (TONE_START_ADDR + (PARAM1_CCNT * \
                                       (TONE_WORD_SIZE >> 3) * PARAM1_BCNT))
#define PARAM2_BCNT                   (((TONE_END_ADDR - PARAM2_START_ADDR) \
                                        / (TONE_WORD_SIZE >> 3)) + 1)

/* AIC3106 codec address */
#define I2C_SLAVE_CODEC_AIC31         (0x18u)//(0x1Bu)

/* McASP Serializer for Transmit */
#define MCASP_XSER_TX                 (1u)//(2u)


/******************************************************************************
**                      INTERNAL FUNCTION PROTOTYPES
******************************************************************************/
static void McASPI2STwoChanConfig(void);

/******************************************************************************
**                      INTERNAL CONSTANT DEFINITIONS
******************************************************************************/
static struct EDMA3CCPaRAMEntry dmaPar[3] = {
       {
           (unsigned int)((0x02 << 8u)),
           (unsigned int)TONE_START_ADDR,
           (unsigned short)(TONE_WORD_SIZE >> 3),
           (unsigned short)PARAM1_BCNT,
           (unsigned int) SOC_MCASP_0_DATA_REGS,
           (short) (TONE_WORD_SIZE >> 3),
           (short)0x00,
           (unsigned short)(32u * 70u),
           (unsigned short)PARAM1_BCNT,
           (short)(TONE_WORD_SIZE >> 3),
           (short)0x00,
           (unsigned short)PARAM1_CCNT
       },
       {
           (unsigned int)((0x02 << 8u)),
           (unsigned int)(PARAM2_START_ADDR),
           (unsigned short)(TONE_WORD_SIZE >> 3),
           0,
           (unsigned int) SOC_MCASP_0_DATA_REGS,
           (short)(TONE_WORD_SIZE >> 3),
           (short)0x00,
           (unsigned short)(32u * 71u),
           (unsigned short)0,
           (short)0x00,
           (short)0x00,
           (unsigned short)(1u)
       },
       {
           (unsigned int)((0x02 << 8u)),
           (unsigned int)TONE_START_ADDR,
           (unsigned short)(TONE_WORD_SIZE >> 3),
           (unsigned short)PARAM1_BCNT,
           (unsigned int) SOC_MCASP_0_DATA_REGS,
           (short) (TONE_WORD_SIZE >> 3),
           (short)0x00,
           (unsigned short)(32u * 70u),
           (unsigned short)PARAM1_BCNT,
           (short)(TONE_WORD_SIZE >> 3),
           (short)0x00,
           (unsigned short)PARAM1_CCNT
       }
};

/******************************************************************************
**                          FUNCTION DEFINITIONS
******************************************************************************/
/*
** Configures the McASP Transmit Section for 2 channels in I2S mode.
*/
static void McASPI2STwoChanConfig(void)
{
    McASPTxReset(SOC_MCASP_0_CTRL_REGS);

    /* Enable the FIFOs for DMA transfer */
    McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

    /* Set I2S format in the transmitter/receiver format units */
    McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, TONE_WORD_SIZE, TONE_SLOT_SIZE,
                     MCASP_TX_MODE_DMA);

    McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
                        MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

    /* configure the clock for transmitter */
    McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
    McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
    McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
                          0x00, 0xFF);

    /* Enable the transmitter/receiver slots. I2S uses 2 slots */
    McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS_L_R);

    /* Set the serializer as transmitter */
    McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

    /*
    ** Configure the McASP pins
    ** Input - Frame Sync, Clock and Serializer 12
    ** Output - Serializer 11 is connected to the input of the codec
    */
    McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
    McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_TX)
                                                | MCASP_PIN_AFSX
                                                | MCASP_PIN_ACLKX
                                                | MCASP_PIN_AHCLKX);
    McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,  MCASP_PIN_AXR(0));
    
//    McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_TX));
//    McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,  MCASP_PIN_AFSX
//                                               | MCASP_PIN_ACLKX);
}

/*
** Activates the data transmission/reception
** The DMA parameters shall be ready before calling this function.
*/
void ToneLoopStart(void)
{
    /* Start the clocks */
    McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);

    /* Enable EDMA for the transfer */
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
                        EDMA3_TRIG_MODE_EVENT);

    /* Activate the  serializers */
    McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

    /* Activate the state machines */
    McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

/*
** Function to initialize the audio codec
*/
void AudioCodecInit(void)
{
    volatile unsigned int delay = 0xFFF;

//    I2CInit(I2C_1);
//    /* Initialize the I2C interface for the codec AIC31 */
//    I2CMasterSlaveAddrSet(SOC_I2C_1_REGS, I2C_SLAVE_CODEC_AIC31);

    AIC31Reset(SOC_I2C_1_REGS);
 //   while(delay--);
    Osal_delay(delay);
    
    AIC3120_Config(SOC_I2C_1_REGS);
    
    /* Configure the data format and sampling rate */
//    AIC31DataConfig(SOC_I2C_1_REGS, AIC31_DATATYPE_I2S, TONE_SLOT_SIZE, 0);
//    AIC31SampleRateConfig(SOC_I2C_1_REGS, AIC31_MODE_BOTH, TONE_SAMPLE_RATE);
//
//    /* Initialize both ADC and DAC */
//    AIC31ADCInit(SOC_I2C_1_REGS);
//    AIC31DACInit(SOC_I2C_1_REGS);
}

/*
** Function to initialize the looping of tone.
*/
void ToneLoopInit(void)
{
    EDMA3Init(SOC_EDMA30CC_0_REGS, 0);

    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                        EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);

    /*
    ** To maintain portability, between GCC and TMS470, we initialize the
    ** BCNT for dmaPar[1] here. Else if the initialization is done above,
    ** TMS470 throws up error: expression must have a constant value
    */
    dmaPar[1].bCnt = PARAM2_BCNT;

    /* Initialize the DMA parameters */
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[0])));
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 70,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[1])));
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 71,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[2])));

    /* Configure the McASP for I2S with two channels */
    McASPI2STwoChanConfig();
}


void ToneLoopdeInit(void)
{
  volatile unsigned int delay = 0xFFF;

  McASPTxReset(SOC_MCASP_0_CTRL_REGS);

  /* Disable EDMA for the transfer */
  EDMA3DisableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
                          EDMA3_TRIG_MODE_EVENT);

  EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                  EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT, EDMA3_CHA_MCASP0_TX,0);

  EDMA3Deinit(SOC_EDMA30CC_0_REGS, 0);

  //AIC31Reset(SOC_I2C_REGS);

  //IntSystemDisable(SYS_INT_I2CINT);
  //IntUnRegister(SYS_INT_I2CINT);

  /* Put i2c in reset/disabled state */
  //I2CMasterDisable(SOC_I2C_REGS);

  while(delay--);
}



int Audio_Test(void)
{
    /* Enable the module clock for McASP0 Instance. */
    McASP0ModuleClkConfig();
    
    /* Enable the EDMA module clocks. */
    EDMAModuleClkConfig();
    
    McASP0PinMuxSetup();
    
    /* Configure the Codec for I2S mode */
    AudioCodecInit();

    /* Initialize the looping of tone. */
    ToneLoopInit(); 

    /* Start playing tone. */
    ToneLoopStart();
  
    while(1)
    {
    }
}
/***************************** End Of File ***********************************/

                    McASP Register Dump Values         

 Revision Identification Register         :0x44307b02  

 Power Idle SYSCONFIG Register            :0x2  

 Pin Function Register                    :0x0  

 Pin Direction Register                   :0x1c000002  

 Pin Data Output Register                 :0x0  

 Pin Data Input Register                  :0x10000002  

 Pin Data Clear Register                  :0x0  

 Global Control Register                  :0x1f00  

 Audio Mute Control Register              :0x0  

 Digital Loopback Control Register        :0x0  

 DIT Mode Control Register                :0x0  

 Receiver Global Control Register         :0x1f00  

 Receive Format Unit Bit Mask Register    :0x0  

 Receive Bit Stream Format Register       :0x0  

 Receive Frame Sync Control Register      :0x0  

 Receive Clock Control Register           :0x20  

 Receive High-Frequency Clock Control Register    :0x8000  

 Receive TDM Time Slot 0-31 Register       :0x0  

 Receiver Interrupt Control Register       :0x0  

 Receiver Interrupt Control Register       :0x0  

 Receiver Status Register                  :0x104  

 Current Receive TDM Time Slot Register    :0x0  

 Receive Clock Check Control Register      :0x0  

 Receiver DMA Event Control Register       :0x0  

 Transmitter Global Control Register       :0x1f00  

 Transmit Format Unit Bit Mask Register    :0xffff  

 Transmit Bit Stream Format Register       :0x18074  

 Transmit Frame Sync Control Register      :0x112  

 Transmit Clock Control Register           :0xe0  

 Transmit High-Frequency Clock Control Register   :0x8000  

 Transmit TDM Time Slot 0-31 Register      :0x3  

 Transmitter Interrupt Control Register     :0x0  

 Transmitter Status Register               :0x58  

 Current Transmit TDM Time Slot Register   :0x0  

 Transmit Clock Check Control Register      :0x5ff0005  

 Transmitter DMA Event Control Register     :0x0  

 DITCSRA_0 Register                         :0x0  

 DITCSRA_1 Register                         :0x0  

 DITCSRA_2 Register                         :0x0  

 DITCSRA_3 Register                         :0x0  

 DITCSRA_4 Register                         :0x0  

 DITCSRA_5 Register                         :0x0  

 DITCSRB_0 Register                         :0x0  

 DITCSRB_1 Register                         :0x0  

 DITCSRB_2 Register                         :0x0  

 DITCSRB_3 Register                         :0x0  

 DITCSRB_4 Register                         :0x0  

 DITCSRB_5 Register                         :0x0  

 DITUDRA_0 Register                         :0x0  

 DITUDRA_1 Register                         :0x0  

 DITUDRA_2 Register                         :0x0  

 DITUDRA_3 Register                         :0x0  

 DITUDRA_4 Register                         :0x0  

 DITUDRA_5 Register                         :0x0  

 DITUDRB_0 Register                         :0x0  

 DITUDRB_1 Register                         :0x0  

 DITUDRB_2 Register                         :0x0  

 DITUDRB_3 Register                         :0x0  

 DITUDRB_4 Register                         :0x0  

 DITUDRB_5 Register                         :0x0  

 DITUDRB_0 Register                         :0x0  

 DITUDRB_1 Register                         :0x0  

 DITUDRB_2 Register                         :0x0  

 DITUDRB_3 Register                         :0x0  

 DITUDRB_4 Register                         :0x0  

 DITUDRB_5 Register                         :0x0  

 SRCTL_0 Register                           :0x0  

 SRCTL_1 Register                           :0x11  

 SRCTL_2 Register                           :0x0  

 SRCTL_3 Register                           :0x0  

 SRCTL_4 Register                           :0x0  

 SRCTL_5 Register                           :0x0  

 XBUF_0 Register                            :0x0  

 XBUF_1 Register                            :0x0  

 XBUF_2 Register                            :0x0  

 XBUF_3 Register                            :0x0  

 XBUF_4 Register                            :0x0  

 XBUF_5 Register                            :0x0  

 RBUF_0 Register                            :0x0  

 RBUF_1 Register                            :0x0  

 RBUF_2 Register                            :0x0  

 RBUF_3 Register                            :0x0  

 RBUF_4 Register                            :0x0  

 RBUF_5 Register                            :0x0  

 Write FIFO Control Register                :0x206438  

 Write FIFO Status Register                 :0x0  

 Read FIFO Control Register                 :0x0  

 Read FIFO Status Register                  :0x0  







                 AUDIO CODEC REGISTER DUMP VALUES


 *********** Page ZERO selected ***********


 Clock-Gen Muxing Register address:0x04             value:0x3  

 PLL J-Value register address:0x06                  value:0x8  

 PLL D-Value MSB register address:0x07              value:0x0  

 PLL D-Value LSB register address:0x08              value:0x0  

 PLL P and R Values register address:0x05           value:0x91  

 DAC NDAC_VAL register address:0x0b                 value:0x88  

 DAC MDAC_VAL register address:0x0c                 value:0x82  

 DAC DOSR_VAL MSB register address:0x0d             value:0x0  

 DAC DOSR_VAL LSB register address:0x0e             value:0x80  

 Codec Interface Control register address:0x1b      value:0x0  

 DAC Processing Block  register address:0x3c        value:0x10  


 *************** Page Eight selected ********


 DAC Coefficient RAM Control register address:0x01  value:0x4  


 ************* Page One selected ************************


 Headphone Drivers register address:0x1f            value:0x86  

 HP Output Drivers POP Removal Settings register address:0x21     value:0x4e  

 HP DAC Output Mixer Routing register address:0x23     value:0x40  

 Class-D Output Driver Driver register address:0x2a    value:0x1d  

 Headphone Drivers register address:0x1f               value:0x86  

 Class-D Speaker Amplifier register address:0x20       value:0xc6  

 Analog Volume to HPOUT register address:0x24          value:0x92  

 Analog Volume to Class-D Output Driver register address:0x26  value:0x92  


 ********************** Page zero selected *******************


 DAC Data-Path Setup register address:0x3f             value:0x94  

 DAC Volume Control register address:0x41              value:0xd4  

 DAC Volume Control register address:0x40              value:0x4  

#Audio Codec (TLV320AIC3120) Register Configuration
#--------------------------------------------------
#w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# ==> comment delimiter

#Set register page to 0
w 30 00 00
#Initiate SW reset
> 01
#Program PLL clock dividers P, J, D, R (if PLL is used)
#PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
w 30 06 08
> 00
> 00
#Power up PLL (if PLL is used)
#PLL Power up, P = 1, R = 1
w 30 05 91
#NDAC is powered up and set to 8
w 30 0b 88
#MDAC is powered up and set to 2
w 30 0c 82
#Program OSR value
#DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
w 30 0d 00
> 80
#Program I2S word length if required (16, 20, 24, 32 bits) and master mode (BCLK and WCLK are outputs)
#mode is i2s, wordlength is 16, slave mode
w 30 1b 00
#select DAC DSP Processing Block PRB_P16
w 30 3c 10
w 30 00 08
w 30 01 04
w 30 00 00
#Set register page to 1
w 30 00 01
#Program common-mode voltage (defalut = 1.35 V)
w 30 1f 04
#Program headphone-specific depop settings (in case headphone driver is used)
#De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4e
#Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
#DAC routed to HPOUT
w 30 23 40
#Unmute and set gain of output driver
#Unmute HPOUT, set gain = 0 db
w 30 28 06
#Unmute Class-D, set gain = 18 dB
w 30 2a 1c
#Power up output drivers
#HPOUT powered up
w 30 1f 82
#Power-up Class-D drivers
w 30 20 c6
#Enable HPOUT output analog volume, set = -9 dB
w 30 24 92
#Enable Class-D output analog volume, set = -9 dB
w 30 26 92
#Set register page to 0
w 30 00 00
#Powerup DAC (soft step enabled)
w 30 3f 94
#DAC gain = -22 dB
w 30 41 d4
#Unmute DAC and Volume Control
w 30 40 04