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TAS5754M: Asking for the TAS5754 MCLK support

SHH
Mastermind 32626 points

Part Number: TAS5754M
Other Parts Discussed in Thread: TAS5756MDCAEVM, , TAS5756M

Hi Team,
Customer is designing the TAS5754. They are some noise issues on customer board. (play 1k tone from NB, the TAS5754 output the robot sound mixed with the normal 1k tone)

The Audio source waveform is perfect that verified by scope. The I2C command is coorect which verified by EVM I2C host.


We found the audio source frequency on MCLK is 3.072MHz.

The audio source send the out the frequency as follow.
The MCLK and BCLK did not tie together.
Can you please check the MCLK can support 3.072MHz? What will happen if customer using the following audio source?

1. MCLK: 3.072MHz
2. BLCK: 3.072MHz
3. WCLK: 48KHz


Thanks,
SHH

  • 0
    TI__Guru 52115 points
    Hi Scott,

    I just did a quick test. My TAS5756MDCAEVM can work with the clocks you mentioned.
    a) MCLK = 3.072MHz
    b) BLCK = 3.072MHz
    c) LRCLK = 48KHz

    Andy
  • 0 in reply to Andy Liu (BMS)
    TI__Mastermind 32626 points

    Hi Andy,
    Thanks a lot for verifying on the EVM board. But it is more concern on what if customer do not follow the table 2 recommendation? Will that has the slight fail rate as customer's situation?

    1. Due to the customer's board is not always has the robot sound, the board fail rate is around 2.5% among 37 pcs PCB.
    2. The fail PCB need to test around 10 times can duplicate the robot sound issues. the fail rate on the fail board is around 5~10%.
    3. Once the issues occurred, customer need to restart the whole OS. then, the issues can fix.

    So the issues is not always happen on the 2.5% fail board. Once normal, the sound keep normal. the the fail is 2.5%*5%~2.5%*10%=0.125%~0.25% 

    Questions:
    1. Do we have concern  or gaurantee for the MCLK to set to 3.072 for this fail sound issues due to the spec is not support for the 64fs sampleing rate from table 2? 
    2. TAS5754 can set the 3 wires, what will happen if customer did not disable MCLK detect at beginning? I am asking customer to provide the I2C registers setting.
    3.Could I know why do you change the MCLK to 3.072MHz? change the EEPROM bin directly or use externally MCLK?

    Thanks,
    SHH

  • 0 in reply to SHH
    TI__Guru 52115 points

    Hi Scott,

    See my comments below.

    1. Do we have concern  or gaurantee for the MCLK to set to 3.072 for this fail sound issues due to the spec is not support for the 64fs sampleing rate from table 2?

    [Andy]: I guess that concern is reasonable since in the TAS5754M datasheet we state that the minimum MCLK frequency supported is 128*fs.  


    2. TAS5754 can set the 3 wires, what will happen if customer did not disable MCLK detect at beginning? I am asking customer to provide the I2C registers setting.

    [Andy]:  I would also suggest your customer try 3-wire I2S if their MCLK frequency cannot be at least 128*fs.

    The script below shows how to enable 3-wire I2S in TAS5756M.

    # Enable 3-wire I2S for Device A

    # Select Page 0
    w 98 00 00
    # Set the device into standy
    w 98 02 10
    # PLL reference clock = BCK (no SCK present)
    w 98 0D 10
    # Ignore SCK halt detection (no SCK present)
    w 98 25 08
    # Wake from standy
    w 98 02 00

    3.Could I know why do you change the MCLK to 3.072MHz? change the EEPROM bin directly or use externally MCLK?

    [Andy]:  I select PSIA in the PPC2 GUI.

     

    Andy