TLV320AIC3206: Analog input common mode not driven correctly

Hi, Anthony,

Welcome to E2E, Thanks for your interest in our products!.

From the schematic's perspective, the circuit seems fine. The common mode in the input pins will be present once the inputs are routed to the internal PGA and the ADCs are powered up. Can you please try this?. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

Thanks for your reply. We have IN2 L/R routed to the left PGA through 10k resistance, and IN1 L/R routed to the right PGA through 10k resistance. We have confirmed that our ADCs are powered up, but the problem still presented.

Through some further testing, we swapped the [47uF ceramic] ac-coupling caps out for 1uF ceramic caps. That seems to have helped a bit - we are able to see roughly 0.9V DC on the codec side of those caps, but it still seems to take some time (more than a few ms) to charge them, and we've noticed that sometimes disconnecting and then reconnecting inputs from the PGA in the routing registers gets things charged up a bit better.

Is there any guidance you can offer on what value and/or type of caps are best suited for this application, without killing the low frequencies in the audio spectrum? Additionally, is there a specific order that we should be bringing things up in software initialization? I've attached our init function for reference. Specifically wondering if it's better to route & then power, or vice versa?

/* Input clock is 24.576 MHz
     * P-divider: 2, R-divider: 1
     */
    snd_soc_write(codec, AIC32X4_PLLPR, 0x21);
    /* PLL J=7 */
    snd_soc_write(codec, AIC32X4_PLLJ, 0x07);
    /* PLL D MSB */
    snd_soc_write(codec, AIC32X4_PLLDMSB, 0x00);
    /* PLL D LSB */
    snd_soc_write(codec, AIC32X4_PLLDLSB, 0x00);
    /* Power Up PLL: P-divider: 2, R-divider: 1 */
    snd_soc_write(codec, AIC32X4_PLLPR, 0xA1);

    /* NADC */
    snd_soc_write(codec, 0x12, 0x87);
    /* MADC */
    snd_soc_write(codec, 0x13, 0x82);
    /* Set OSR for ADC to 128 */
    snd_soc_write(codec, 0x14, 0x80);

    /* NDAC divider to 7 */
    snd_soc_write(codec, 0x0B, 0x87);
    /* MDAC divider to 2 */
    snd_soc_write(codec, 0x0C, 0x82);
    /* Set OSR for DAC to 128 (MSB) */
    snd_soc_write(codec, 0x0D, 0x00);
    /* Set OSR for DAC to 128 (MSB) */
    snd_soc_write(codec, 0x0E, 0x80); /* 0x80 = d128 */

    /* Select ADC PRB_R1 PRB_R1 */
    snd_soc_write(codec, 0x3d, 0x01);

    /* Disable Internal Crude AVdd in presence of external AVdd supply: 0x08
     * with 0x2 to power up charge pump
     */
    snd_soc_write(codec, AIC32X4_PWRCFG, 0x0A);

    /* Enable Master Analog Power Control */
    snd_soc_write(codec, AIC32X4_LDOCTL, 0x00);

    /* Set the input common mode to 0.9V */
    /* Enable gnd_sense */
    snd_soc_write(codec, AIC32X4_CMMODE, 0x00);

    /* Select ADC PTM_R4 */
    snd_soc_write(codec, AIC32X4_ADCPOWERTUNECONG, 0x00);
    /* Set MicPGA startup delay to 3.1ms */
    snd_soc_write(codec, AIC32X4_AIQCCONG, 0x32);
    /* Set the REF charging time to 40ms */
    snd_soc_write(codec, AIC32X4_REFPOWERUPCONF, 0x01);

    /* Enable headphone to be ground-centered (requires charge pump above) */
    snd_soc_write(codec, AIC32X4_HEADPHONECONF, 0x10);
    /* Enable the Mixer Amplifiers and Headphone Amplifiers */
    snd_soc_write(codec, AIC32X4_OUTPWRCTL, 0x33);

    /* Codec clk is PLL clock output; PLL clock input is MCLK pin. */
    snd_soc_write(codec, 0x04, 0x03);
    /* I2S configured for 24-bit word, master mode */
    snd_soc_write(codec, 0x1b, 0x2C);
    /* I2S Audio Interface Settings: setting BCLK_DIV src to ADC_MOD_CLK */
    snd_soc_write(codec, 0x1d, 0x03);
    /* I2S: BCLK_DIV powered up and divide by 2 */
    snd_soc_write(codec, 0x1e, 0x82);
    /* I2S: WCLK Output from Generated */
    snd_soc_write(codec, 0x21, 0x10);
    /* I2S: DOUT is Prinary DOUT on DOUT/MFP2 */
    snd_soc_write(codec, 0x35, 0x12);

    /* Left MICPGA Volume; MSB=1 (enable), MSB=0 (0dB); lowest 7 bits linear range from 000_0000=0dB to 101_1111=47.5dB */
    snd_soc_write(codec, AIC32X4_LMICPGAVOL, AIC32X4_GAIN);
    /* Right MICPGA Volume; MSB=1 (enable), MSB=0 (0dB); lowest 7 bits linear range from 000_0000=0dB to 101_1111=47.5dB */
    snd_soc_write(codec, AIC32X4_RMICPGAVOL, AIC32X4_GAIN);

    /* Page 1 / Register 52: Left MICPGA Positive Terminal Input Routing Configuration */
    /* IN2L is routed to Left MICPGA with 10K resistance */
    snd_soc_write(codec, AIC32X4_LMICPGAPIN, 0x10);
    /* Page 1 / Register 54: Left MICPGA Negative Terminal Input Routing Configuration */
    /* IN2R is routed to Left MICPGA with 10K resistance */
    snd_soc_write(codec, AIC32X4_LMICPGANIN, 0x10);

    /* Page 1 / Register 55: Right MICPGA Positive Terminal Input Routing Configuration */
    /* IN1R is routed to Right MICPGA with 10K resistance */
    snd_soc_write(codec, AIC32X4_RMICPGAPIN, 0x40);
    /* Page 1 / Register 57: Right MICPGA Negative Terminal Input Routing Configuration */
    /* IN1L is routed to Right MICPGA with 10K resistance */
    snd_soc_write(codec, AIC32X4_RMICPGANIN, 0x10);

    /* Page 1 / Register 58: Floating Input Configuration Register - 0x01 / 0x3A */
    snd_soc_write(codec, AIC32X4_FLOATINGINPUT, 0x00);

    /* MAL to HPL */
    snd_soc_write(codec, AIC32X4_HPLROUTE, 0x02);
    /* MAR to HPR */
    snd_soc_write(codec, AIC32X4_HPRROUTE, 0x02);

    /* HPL Driver Gain Setting Register */
    snd_soc_write(codec, AIC32X4_HPLGAIN, AIC32X4_HP_DRIVER_GAIN);
    /* HPR Driver Gain Setting Register */
    snd_soc_write(codec, AIC32X4_HPRGAIN, AIC32X4_HP_DRIVER_GAIN);

    /* Power up and down and up Left and Right ADC Channels */
    snd_soc_write(codec, 0x51, 0xc0);

    /* Power up and down and up left and right DAC channels */
    snd_soc_write(codec, 0x3F, 0xc5);

    /* Unmute Left and Right ADC Digital Volume Control and fine gain */
    snd_soc_write(codec, 0x52, 0x00);

    reg = snd_soc_read(codec, AIC32X4_ADCFLAG);
    pr_info("ADC Flag Register 0x%X\n",reg);