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TLV320AIC3104: Power Consumption optimization

Alberto Soattin
Genius 16905 points
Part Number: TLV320AIC3104
Other Parts Discussed in Thread: TLV320AIC3105

Hi Support,

my customer is trying to optimize power consumption on TLV320AI3104. In  their design they are using two codecs. The first one is used for gathering data from ADC, transferring them though SAI interface and then playing from SAI via Hi-power outputs to amplifier for speaker output.

Specification of setup and interface: Sai: I2S mode, stereo mode, Audio Frequency 16khz.

 Setup is the following:               

Register:

value:

3

0x91

4

0x60

5

0x00

6

0x00

11

0x01

101

0x00

2

0x44

7

0x0A

43

0x02

37

0xE0

41

0xA2

38

0x10

46

0x00

49

0x00

63

0x0D

51

0x0D

19

0x07

22

0x07

15

0x20

16

0x20

 

 

Total power consumption of this setting is about 12mA. This is value get after everything was setup, but no clocks were provided.

 

 

The second one is used as amplifier only. Here is input amplified by PGA and sent to Hi-power outputs to ADC of MCU.

 Specification of setup for second codec:

Register:

value:

8

0x20

7

0x00

41

0x02

43

0x80

37

0x20

38

0x10

46

0x80

49

0x80

51

0x0D

63

0x0D

19

0x03

22

0x03

15

0x20

16

0x20

 

Looking into TLV320AIC3104 SLAS510F part 8.6 Electrical Characteristics table is:

 

From that, I would expect that codec’s consumption should be 3.11mA + HP-output which is about 2mA for each channel. In total, it is about 7 mA. But theyare still getting 9.77mA in total.

Can you please help me understanding why the power consumption is higher than expected?

 Thanks and regards,

Alberto

  • 0
    TI__Mastermind 30090 points
    Hi Alberto,

    I am checking in with the systems team to confirm the routing for this measurement.

    can you tell me what the current draw is if they power down the PGA blocks but keep everything else the same?

    best regards,
    -Steve Wilson
  • 0
    TI__Mastermind 30090 points

    Alberto, 

    This is a Datasheet error.  The AIC3104 is a simplified version of the AIC3106, and thus the datasheet for the AIC3106 was likely used as a starting point. In the AIC3106 there are 3 bypass path (see below):

    The AIC3104, along with the AIC3101,AIC3107, and AIC3109 do not have the Line2L/R bypass path (highlighted in yellow above),  however this path is described in 10.4.1.1, and the "stereo line in to stereo line out" current consumption spec is for that path.  The design team confirmed that the PGA bypass path (highlighted green) will draw closer to 6ma. If the PGA is not necessary,  The Passive analog bypass path would be the lowest current option, but does not allow for use of any buffers or amplifiers. 

    We will be making these corrections to the AIC310x datasheets in the near future, as all of them contain this error. 

    best regards, 

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Genius 16905 points

    Thanks Steve,

    I would add few comments and details to this topic. We did some deeper analysis and here are our findings:

    About CODEC #2:

    (PGA enabled, I2S mode, stereo mode, Sampling Frequency 16khz)

    • We see that disabling PLL mode (Register 3) can save us about 2mA. The question is what is the purpose of PLL. Some time ago it was recommended to us to use this when we were solving the noise issue. However the resolution for noise was to implement the LP filter on CODEC output. Now it seems to us that we do not need PLL. Can you please confirm this?

    About CODEC #1:

    (PGA enabled and connected to a HP output, no sampling, no SAI enabled)

    • We noticed that enabling the  connection between the PGA and HPout increase current about 3mA for each channel.

    This we do by writing the value 0x80 to the registers 46 and 49

    We do not really understand if this step only connects PGA with HPout  - if yes, why it takes 3mA per channel ?

    Or is this about enabling the PGA? If yes, is there any chance to use PGA with lower power consumtion?

    • Currently we use HPout for both CODEC’s – writing value 0D into registers 51 and 63.

    As the outputs of both CODEC’s are routed into high impedance we think that we could use standard line outputs and save another aprox 1-2mA per channel. Please confirm our idea.

    It would be great if you could find another possibility of saving some power for both CODEC configuration.

    For better understanding I send the schematic page for CODEC’s and also block diagram how the CODEC’s input and output are routed in the system.

    GHP_3x_CODEC_routing_diagram.pdf

    Alberto

  • 0 in reply to Alberto Soattin
    TI__Mastermind 30090 points

    Alberto, 

    regarding Codec #2 :  if they can use the divider instead of the PLL,  that could certainly save them some power.

    regarding codec #1

    The image below shows the summing amplifier that gets activated when you enable R46, R49, R60, and R63. 

    This is what gets powered up when you "connect" PGA_R or PGA_L to HPLOUT or HPROUT. 

    One thing that may help, is changing the configuration of HPLCOM and HPRCOM.  if they make sure that those outputs are configured as independent single ended outputs (R37 and R38) I believe the inverting amplifiers (shown in green)  will not be powered up,  that could end up saving a little.  Note that i modified the block diagram to show the HPL/RCOM inverter circuit more accurately. 

    The only downside of using the LPOUTS is that they are not configurable to SE outputs.  for differential to SE conversion we recommend an active solution (opamp buffer) to ensure no performance degradation. 

    best regards, 

    -Steve wilson

  • 0 in reply to Steve-Wilson
    TI__Mastermind 30090 points
    Alberto,

    I am not sure why I didn't think of this before, but the TLV320AIC3105 DOES have the Line2L/R Bypass path, It is similar to the AIC3104 but with 6 SE inputs rather than 2Differential+2SE inputs.

    so if the lower power stereo line path is important, that may be a better device for them.

    best regards
    -steve Wilson