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PCM3060: Output data sometimes becomes abnormal when sampling rate is changed.

Masanori Tachibana
Genius 5350 points

Part Number: PCM3060

Hello support team,

I have questions regarding PCM3060.
Our customer uses PCM3060 as A/D converter.

The phenomenon that DOUT goes "L" at the timing when sampling frequency of ADC is switched sometimes occurs.

1. Setup procedure and phenomenon

(1) CLK = 18.432 MHz

(2) ADPSV = 0, M / S1 [2: 0] = 3 (fs = 48 kHz)
* Each setting interval is 504.2 μs or less

(3) After about 700 ms elapsed

(4) ADPSV = 1, M / S1 [2: 0] = 1 (fs = 24 kHz), ADPSV = 0
* The setting interval of each is 504.2 μs

(5) DOUT data becomes abnormal and goes "L", and there is no response to the change of Vin.

(6) Once the data becomes abnormal, it will not recover unless the power is turned on again.

2. Question

(1) In the datasheet, it is written that setting to the power down mode is recommended when changing the setting such as sampling rate. Is it a required procedure?
If the customer do not care about pop / click noise, is there any problem if you change the sampling rate while operating the ADC?

(2) Does this phenomenon occur because the power saving time of ADPSV is too short? Or is there another root cause?

(3) If the customer sets the time from ADPSV = 1 to ADPSV = 0 to 2048 / fs, how much time is required from ADPSV = 1 to M/S1[2:0] = 1?
And, how much time is required from M/S1[2:0] = 1 to ADPSV = 0?

Best regards,
M. Tachibana

  • 0
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the explanation of the issue.  Please refer to below:

    1. The change on the fly of the sampling rate might cause noise and performance degradation issues only, it would be a matter of customer to evaluate if the performance of the device is fine for their application if changing the sampling rate without putting the device into power-saving mode is required.
    2. It is possible, the time required for the DOUT to complete properly the fade out process once ADPSV is triggered is about 1936/Fs (40ms for 48KHz) and the part will be at power-down state once this time is elapsed. Once the part is in power down state, the sampling rate can be changed. Before returning to normal operation, ADPSV should be held at high state during a minimum time of 2048/Fs (42ms for 48KHz). 
    3. Changes to M/S1' registers would be recommended after the device is completely in power down mode.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points

    Hello Melendez-san,

    Thank you for your great support.

    Can I understand that changing the data rate without putting into the power down mode is not the cause of data lost?
    If so, what reason is thought that the data will not come out?

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    Genius 5350 points
    Hello Melendez-san,

    Let me ask you additional questions.
    (Some of them might be repeated questions)

    (3) Is my understanding correct?
    The purpose of putting into the power save mode when user changes the audio mode is just recommendation for reduction of output noise. And it is not a restriction on the circuit configuration.

    (4) In the case of setting M/S1[2:0] again, is there any restriction on time?
    For example, between the first setting of M/S1[2:0] and the second setting M/S1[2:0].

    Best regards,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    The recommendation for changing the sampling rate is to avoid noise artifacts and performance degradation when the sampling rate is changed dynamically. As this is not a common use-case, we don't have data to validate that the device will behave without issues after changing sampling rate without entering power-saving mode first. There is no evaluation board available for this device, so it would be complicated to try replicating this problem and verify if effectively changing the sampling rate dynamically does not cause other issues.

    Unfortunately we don't have the exact time required to perform a sampling rate change as a specification of this device. This is a quite old pat and it would be complicated to get the exact timing spec for this use-case. My assumption is that the synchronization time for the clocks should be elapsed before changing the sampling rate of the device (please refer to page 22 of the datasheet). 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points

    Dear Melendez-san,

    Thank you for teaching me.
    I'll advise our customer to put into the power-down mode when switching the sampling rate.

    Thanks for your future support as well.

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    Genius 5350 points
    Dear Melendez-san,

    I'll ask questions about PCM3060 again.
    An abnormal phenomenon that DOUT remains 'L' seemed to occurr even in the case of setting the sampling rate by the following procedure.

    1. Power-up in power down mode. At that time, DOUT remains "L", LRCK and BCK are output.
    2. Set the sampling frequency. Then, LRCK and BCK change according to the sampling frequency.
    3. Release the power down mode and set the normal mode. Then data is output from DOUT.
    4. However, the phenomenon that DOUT goes 'L' occurs immediately.
    *SCL of I2C is 83.3 kHz, and all registers are always written at 3.6 ms cycle.

    However frequency of the abnormal phenomena seem to be decreased.

    [Questions]
    (1) Is there any problem with the above procedure?
    (2) Is it possible to access registers related to audio mode when operating in normal mode?
    (3) Is there any problem that the same value as the previous time is written in the register related to the audio mode when operating in normal mode?

    Best regards,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the feedback. The procedure seems correct, so it is strange that the DOUT is being forced to L state after releasing the power-down mode. There should be no problem with accessing the registers while the part is in normal mode. Do you know if there is something on the DOUT line that could be triggering the signal to low state?. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points

    Hello Melendez-san,

    Thank you for your great support.

    Trigger that fixes DOUT to 'L' has not seem to be found.

    The customer wants to check possible factor exhaustively.
    So he has further questions.

    [Questions]
    (3) Should he think that the state is in normal mode (not in power down mode) in case that DOUT is fixed to 'L' after the procedure explained earlier.

    (4) Is there a possibility to latch up after changing the sampling rate?

    I guess this abnormal condition is neither in the power down mode nor in the latch up state.
    So I am asking the customer to measure the circuit current.

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    Genius 5350 points
    Hello Melendez-san,

    I got new information from the customer.

    The customer examined additional experiments and found out the following newly.

    - The problem occurs even after returning to the normal mode without changing the audio mode.
    - When resetting with the reset pin of PCM3060, the problem occurs or returns to normal state.
    (It is not ON / OFF of power supply, but ON / OFF of reset signal)

    Based on the above results, the customer presume that the cause of the problem is not by the mode change procedure, but reset failure.


    [Additional questions]
    (5) Is there any unapplied pin or signal during reset state?

    (6) Is the release conditions from reset state as follows?
    - 3.3 V of power supply is more than 2.2 V.
    - Reset pulse width is more than 2048 / fs.

    (7) Are there any other conditions?

    (8) Is it OK to release the reset state while inputting analog signal?
    And is it OK to release the reset state while communicating I2C bus?

    Best regards,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    Genius 5350 points

    Hello Melendez-san,

    I appreciate your great support.
    Please let me have further questions.

    (9) Is there any cases that causes problems such as latch-up when PCM3060 is reset or powered on / off with remaining voltage at Vin pin?

    (10) Could you teach me the purpose of adding the diodes at Vin pin such as shown in a) of Figure 34 on page 40 of the datasheet?

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    Genius 5350 points

    Hello support team,

    Our customer wants to solve the problem as soon as possible.
    However, he is in trouble because he can't understand the cause of the problem.
    Would you give me some advice? I really need your help.

    [Questions]
    (3) Should he think that the state is in normal mode (not in power down mode) in case that DOUT is fixed to 'L' after the procedure explained earlier.
    (4) Is there a possibility to latch up after changing the sampling rate?
    (5) Is there any unapplied pin or signal during reset state?
    (6) Is the release conditions from reset state as follows?
      - 3.3 V of power supply is more than 2.2 V.
      - Reset pulse width is more than 2048 / fs.
    (7) Are there any other conditions?
    (8) Is it OK to release the reset state while inputting analog signal?
    And is it OK to release the reset state while communicating I2C bus?
    (9) Is there any cases that causes problems such as latch-up when PCM3060 is reset or powered on / off with remaining voltage at Vin pin?
    (10) Could you teach me the purpose of adding the diodes at Vin pin such as shown in a) of Figure 34 on page 40 of the datasheet?

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Sorry for the delayed reply. As I mentioned previously, this part is quite old and doesn't have an EVM available, so getting detailed information of the behavior of the device is complicated. I will try to address the questions provided, but please consider that it is complicated to provide all the answers without the ability to test this on our end.

    3- It is possible that the issue is occurring in normal mode, but in this mode it is not a normal behavior for the device to send a 'L' value, that's why i suggested to identify a possible external circuit that could be changing this signal. 

    4- As long as the procedure meets the previously discussed timing, I think there should be no issue with the change of sampling rate. 

    5- Reset state is triggered once the /RST signal is set to low value; when the part is in Reset state, the DOUT signal will be forced to "L"value. When the part is configured via software, two reset registers are available apart from the /RST pin. MRST is the mode reset which resets the configuration of the device, while SRST is use to reset the system and perform a re-synchronization. Actually, is it possible that while changing sampling rates, a SRTS reset is required to force the synchronization of the clocks. Can you please try this (set SRST to '0' while in power down mode)?.

    6- Yes, but please consider that the conditions correspond to different Reset states. The power supply value is read during power-on only and triggers the power-on-reset sequence. The duration of the /RST signal should meet the mentioned time to perform a complete  the external reset sequence.

    7- All the required conditions are mentioned on the Power-on-reset and external reset sequence of the datasheet.

    8- This is not a recommended use case as audible artifacts can be heard while the digital output is starting to stream data. For the I²C controls, it is not recommended as the registers will retain their reset value until the sequence has finished. then, the I²C register write should be performed. Releasing reset while configuring the part could lead into incorrect configuration of the device. 

    9- This should not cause the latch problem, possible issues caused are more related to noise artifacts.

    10- The diodes on the mentioned figure are used only for overvoltage protection.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points

    Hello Melendez-san,

    Thank you for your kind support.
    I understood that it is complicated to investigate deeply because this device is old.
    It would be fine if you let me know  as far as you can investigate.

    Our customer has also continued the experiment, and new facts have been found out.

    (1) The problem is recreated even after returning to the normal mode without changing the audio mode.
    (2) When resetting with the RST pin, the problem is resolved or recreated.

    Based on the above, the customer guesses that the problem is not caused by the mode change procedure but reset failure.

    (3) The circuit of the front stage of the analog input of the PCM3060 is as a) of "Application Examples for Analog Input and Output" on the datasheet.
    But no diode is connected.
    The value of resistor and capacitor is as follows.
       R1: 7.5 kΩ
       R2: 7.5 kΩ
       R3: 1 kΩ
       C1: 4.7 μF
       C2: 220 pF
       C3: 10 μF + 0.1 μF

    In this circuit, the discharge of VinX is delayed after the power supply is turned off, and the voltage remains in about several seconds.
    It takes about 24 seconds to decrease from +0.5 V to +0.3 V after turning off the power.
    Probability that trouble will occur goes high if the power is turned on again before the voltage goes down.
    Some boards do not cause any trouble at all.
    The customer had previously configured this circuit with a simple RC filter. At that time, the voltage of VinX pin became 0 V immediately after turning off the power.  And no trouble had occurred.

    (4) After turning off the power supply, and connect a resistor of 10 kΩ to the VinX pin to discharge, the customer removed the resistor and turned on the power supply  again. So the problem occurs only once. The frequency of the problem was lower than when not discharging.

    From the above results, is there anything you can think of?

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the feedback.

    The behavior described when powering the device off is not expected and probably is causing some issues to the ADC of the part. Do you know what is the maximum input voltage provided? As you can see, the recommended gain on the datasheet is 0.5, this is meant to enable the system to accept a 2Vrms input as the maximum supported input on VINx pins is around 1Vrms. The gain on customer's circuit is 1 so it is important to provide a maximum input of 1Vrms to the circuit. Otherwise, the ADC of the device might not work as expected. Is it possible to try using the same values from the recommended circuit of the datasheet?. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points
    Hello Melendez-san,

    I'm very sorry for my late reply.

    We are still discussing with our customers.

    The customer experimented and found out the following things.
    (1) In the condition that 3.3 V of voltatge is added to VDD, no trouble will occur even if VCC is set to 0 V and returned to 5 V.
    (2) In the condition that 5 V of voltage is added to VCC, the trouble may occur if VDD is set to 0V and returned to 3.3 V.
    (3) The trouble may occur after setting pin 15 (RST) to "L" and returning to "H".

    From these result, the customer and I guess that the analog part has no problem and that the reset or the setting of register may be failure.

    By the way, the customer is using at fs = 24 kHz.
    Although fs = 24 kHz is not listed in Table 2 of datasheet, can we use with fs = 24 kHz?

    Best regards,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the feedback. From the information provided, I think the issue is related to the sequence followed to turn the power supplies on.

    In general, VDD and VCC should be stable and set before changing the external reset from low to high. VDD powers the digital section of the device, and VCC the analog section. If the analog section is powered and  the digital section power is changing between on and off,  the analog blocks may latch. Please try a sequence where VDD is provided and then VCC, finally, set RST to high.

    Using a sampling rate of 24KHz might be fine.

    Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points
    Hello Melendez-san,

    Thank you for the advice.

    We will conduct a joint evaluation with the customer next week, so we will check the order of releasing the reset.

    It seems that DOUT goes 'L' only after changing the sampling rate to 24 kHz and restarting PCM3060.
    Yesterday I informed you that the phenomenon depends on the order of turning on / off of the power supply.
    These conditions are also just after changing the sampling rate to 24 kHz.

    So, we suspect mute operation due to clock out of sync in addition to reset malfunction.

    You have advised me to perform a system reset when changing the sampling rate.
    We are asking the customer to do this, and the customer is trying now.

    Best regards,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the feedback. Can you please share the system clock used for the PCM3060?, I wonder if the clock combination of the system clock and the sampling rate selected could be triggering a problem.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points

    Hello Melendez-san,

    Thanks for your suggestion.

    I heard that the frequency of the system clock is 18.432MHz.

    Best regards,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Guru 57800 points

    Hi, Tachibana-san,

    Thanks for the feedback.The system clock provided should operate properly with the intended sampling rate.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Genius 5350 points
    Hello Melendez-san,

    Today, we have done joint evaluation with the customer.

    As a result of the experiment, we found that the reason of the problem was what the time to reset the I2C communication after resetting with the reset pin (pin 15) was short.

    As a result of the experiment, we found that the short time from releasing of the reset (pin 15) to starting I2C communication caused the problem.

    The problem was solved by following countermeasures.
    1. After releasing the reset, 100 ms of time should be waited and I2C communication would be started.
    2. After I2C communication starts, master reset with register setting should be executed first, then desired setting (sampling rate etc.) should be written.
    Even if I repeated 100 times, the phenomenon no longer occurred.

    Thank you for great support.
    Best regards,
    M. Tachibana