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TAS5630B: How is the Pin-to-Pin Short-Circuit protection implemented?

benoit.thebaudeau.dev
Intellectual 320 points
Part Number: TAS5630B

Hi,

We have a design using the TAS5630B in which VDD and GVDD_X rise several seconds before PVDD_X. As the PPSC detection system starts when VDD is supplied, we wonder if this system can detect OUT_X <-> GND_X and OUT_X <-> PVDD_X short circuits in our design (i.e. while PVDD_X are not supplied), or if it will always pass, even with shorts.

In order to answer this, we need to know how the PPSC protection works internally. We think that one possibility is that pulls are enabled while the half bridges are set in the Hi-Z state: during the first (resp. second) step detecting shorts from OUT_X to GND_X (resp. PVDD_X), a pull would be enabled internally between OUT_X and PVDD_X (resp. GND_X), so that the resulting voltage on OUT_X would be PVDD_X (resp. GND_X) with no short and GND_X (resp. PVDD_X) with a short, which would always give 0 V on OUT_X if PVDD_X is not supplied. Another possibility would be to connect VDD to OUT_X with a current limiter and to measure the voltage evolution on OUT_X.

Section "7.3.2.1 Powering Up" in the datasheet states that no power-up sequence is required, but it seems to compare only the supplies of VDD and GVDD_X while ignoring PVDD_X. Please clarify.

This section also states that it is not required (though recommended) to hold /RESET low while powering up the device. However, if we supply VDD and GVDD_X with /RESET low, then release /RESET, then only supply PVDD_X, we sometimes get unexpected overcurrents making the amplifier unusable. If we release /RESET only after having supplied VDD, GVDD_X, and PVDD_X, then everything always works fine.

  • 0
    TI__Guru 65320 points
    Hello,

    RESET should never be enabled until all supplies are up and stable.

    Basically what PPSC does is try to pull each output high (to check for short to GND) and low (to check for short to PVDD) using a small current internal to the device (not the output FETs). Without PVDD this PPSC check cannot pass and therefore the device will just sit there and retry the PPSC indefinitely.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Intellectual 320 points
    If the PPSC check cannot pass until there are both PVDD and no shorts, we should always see /SD asserted during that time in our design. However, during that time, we get a stable /SD, but it is not always asserted (i.e. its state is random from one power-on to another). How do you explain that?
  • 0 in reply to benoit.thebaudeau.dev
    TI__Guru 65320 points
    Please explain exactly the bring up sequence in which you see this behavior?

    Also please share your schematic.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Intellectual 320 points

    Thanks for your quick reply.

    Adam Sidelsky said:
    Please explain exactly the bring up sequence in which you see this behavior?

    1. At t = 0 s :
      • /RESET is held low.
      • The audio inputs are kept silent.
      • PVDD is off. Note that there may be a residual voltage at this point on PVDD if the board is power-cycled quickly (big capacitors not fully discharged).
      • VDD and GVDD are brought up simultaneously to 12 V.
    2. After VDD and GVDD are supplied, /SD and /CLIP are either both low or both high.
    3. At t = 4 s, PVDD rises to 30 V.
    4. Then, the system waits until /SD is deasserted (let's say this happens at t4).
    5. At t = t4 + 1 s, /RESET is released.
    6. Then, the system waits until READY is asserted to raise the volume of the audio inputs progressively up to its nominal level.

    Adam Sidelsky said:
    Also please share your schematic.

    I will check if I am allowed to give it. Is there a way of sending it as a private message? There's really nothing fancy. It closely follows the datasheet. The TAS is controlled by an MCU and a DSP, and there is a FET to switch PVDD on or off.

    Regards,
    Benoît

  • 0 in reply to benoit.thebaudeau.dev
    TI__Guru 65320 points
    Benoit,

    Thanks for the explanation. You can send me the schematic at adamsidelsky(at)ti(dot)com and I will review it.

    Where in your steps numbered above is the issue you mention:
    "If the PPSC check cannot pass until there are both PVDD and no shorts, we should always see /SD asserted during that time in our design. However, during that time, we get a stable /SD, but it is not always asserted (i.e. its state is random from one power-on to another):"

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Intellectual 320 points

    Adam,

    Thanks. I'll see on Monday for the schematic.

    This issue is right from the beginning, in step 2. According to what you said about the PPSC check, we should always see /SD asserted from step 2 to step 3, i.e. from the rise of VDD and GVDD (beginning of the PPSC check) until a very short time after the rise of PVDD (end of the PPSC check, which can eventually pass with PVDD), assuming that there are no shorts. This inconsistent behavior is weird and maybe a clue that something is wrong (perhaps PVDD should never be raised after VDD and GVDD), so we'd like to be sure about what should be done here, and also we'd like to make sure that the PPSC check works in our design if a short happens (we'd better not test this, all the more the behavior might not be consistent if we did something wrong), but apart from these doubts, our design works fine.

    Regards,
    Benoît

  • 0 in reply to benoit.thebaudeau.dev
    Intellectual 320 points

    Adam,

    The /CLIP behavior at power on was caused by a glitch in the control logic of PVDD. This is now fixed.

    Regarding /SD, the behavior is still the same. I attach waveforms showing the two observed startup sequences. You can open them with Saleae Logic (www.saleae.com/downloads) or use the CSV exports.

    I've now solved the conundrum: the behavior of /SD at power on depends on the residual voltage on PVDD. If it is less than about 1.4 V, then /SD remains low until PVDD rises for good, which corresponds to the behavior of the PPSC check that you described, i.e. failing in a loop until there are both PVDD and no pin-to-pin shorts. Otherwise (PVDD >= 1.4 V at power on), /SD rises immediately and remains high, which means that the residual voltage on PVDD was high enough for the PPSC check to pass. In the latter case (PPSC check passing with a residual voltage on PVDD), is there any risk of a false negative (i.e. no shorts detected in the presence of shorts) because PVDD is not stable?

    Regards,
    Benoît

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/6/TAS5630B-Startup.7z