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TLV320ADC3101: Is there any behavioural functional model available for a given configuration of the I2S?

Cian Rafferty
Prodigy 70 points
Part Number: TLV320ADC3101

Hi,

The TLV320ADC3101 supports a TDM + DSP multi-channel configuration of the i2s.

By connecting up 4 ADCs (1 master, 3 slave) and programming the various registers as follows (ADC udio interface control, i2s tdm control, data slot offset 1, data slot offset 2) over i2c, the expected i2s frame structure should be similar to the following:

Is there a model available of the ADC which will produce an expected i2s output depending on a given configuration, either in System verilog or C? 

I have a configuration for the 4 ADCs which should produce the above output, but if possible would like to validate that config against a model of the TLV320ADC3101 part.

Any help here would be really appreciated.

Thanks,

Cian

  • 0
    TI__Guru 57800 points

    Hi, Cian,

    Welcome to E2E, Thanks for your interest in our products!.

    Unfortunately, we don't have a model like the one you are requesting. We have an app note where the configuration of the 'ADC3101 is explained for multi-channel applications, perhaps you can use it as reference.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points

    Hi Diego,

    Thanks for the quick response! Thats unfortunate about a model, but thank you for the document in any case.

    Would you be able to validate that the above i2s frame structure will be produced by the following programming of the audio related registers (after the synchronization of clocks, and setting up of dividers is completed):

    M0 (Analogous to device #1 in app note Figure 1.) 

            Reg 0x1B, Value 0x7D, => ADC Audio Interface Control 1

    ADC interface = DSP
    ADC interface word length = 32 bits
    BCLK is output.
    WCLK is output.
    3-stating of DOUT

            Reg 0x26, Value 0x03, => I2S TDM Control Register

    Channel swap disabled
    Both left and right channels enabled
    early_3-state enabled
    time_slot_mode enabled (2 channels controlled by 2 separate offsets)

            Reg 0x1c, Value 0x01, => Data Slot Offset Programmability 1 (Ch_Offset_1)

    Offset = 1 BCLKs (offset measured with respect to the WCLK rising edge in DSP mode)

            Reg 0x25, Value 0x01, => Data Slot Offset Programmability 2 (Ch_Offset_2)

    Offset = 1 BCLKs (offset measured with respect to end of the first channel)

    S1 (device #2)

            Reg 0x1B, Value 0x71, => ADC Audio Interface Control 1

    BCLK is input
    WCLK is input
    3-stating of DOUT

    Reg 0x26, Value 0x03,

    Reg 0x1c, Value 0x43, => 67 Bclks

    Reg 0x25, Value 0x01, => 1 Bclks

    S2 (device #3)

            Reg 0x1B, Value 0x71, => ADC Audio Interface Control 1

    BCLK is input
    WCLK is input
    3-stating of DOUT

    Reg 0x26, Value 0x03,

    Reg 0x1c, Value 0x85, => 133 Bclks

    Reg 0x25, Value 0x01, => 1 Bclks

     

    S3 (device #4 if one existed)

            Reg 0x1B, Value 0x71, => ADC Audio Interface Control 1

    BCLK is input
    WCLK is input
    3-stating of DOUT

    Reg 0x26, Value 0x03,

    Reg 0x1c, Value 0xC7, => 199 Bclks

    Reg 0x25, Value 0x01, => 1 Bclks

     


    Thanks,

    Cian

  • 0 in reply to Cian Rafferty
    TI__Guru 57800 points

    Hi, Cian,

    Thanks for the feedback, I took a look to the register settings. The only issue i found is that the clocking scheme provided seems to have an extra offset, in DSP mode, the data is streamed right after the WCLK transition, so in order to meet your clock structure, an extra offset will be required on Channel 1 of all the devices.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points

    Hi Diego,

    Yes, thans for spotting that. I think the new waveform below should correct this:

    Thanks very much again for the help,

    Cian

  • 0 in reply to Cian Rafferty
    TI__Guru 57800 points

    Hi, Cian,

    Thanks for sharing the clock diagram, it is correct now and matches the configuration for the ADCs discussed before.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points

    Hi Diego,

    Great. Thanks again for all your help!

    Cian

  • 0 in reply to Diego Melendez
    Prodigy 70 points

    Hi Diego,

    Sorry to reopen this, but I just wanted to be clear on something. With the given configuration, there wont be any breaks between a full tdm transaction as shown below?

    Thanks,

    Cian

  • 0 in reply to Cian Rafferty
    TI__Guru 57800 points

    Hi, Cian,

    It will depend on the number of bit clocks between each word clock. For example, if you are using 3 stereo devices with 32-bit configuration, based in your current scheme each channel will take 33 bits (32 of data + 1 offset), so the total number of bits used would be 198 (33×6).

    If bit clock is configured as 198×Fs, there will be no space between transactions as the total of bits would be used. If you need a 1-bit space between transactions, a 199×Fs bit clock would be required.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points
    Hi Diego,

    Question 1:
    Which register is used to program the number of bit clock (num x Fs)?

    Question 2:
    If we take it as 4 devices as opposed to 3 as described in the diagram, by your explanation 33x8 = 264 BCLKs would be needed to replicate the above diagram assuming data width = 32 bits.
    And 33x8 + 1 = 265 BCKs to reproduce the timing diagram at the start of this thread.
    Can you confirm this?

    Thanks a lot again,
    Cian
  • 0 in reply to Cian Rafferty
    TI__Guru 57800 points

    Hi, Cian,

    In the Master device of the I²S bus, the bit clock is divided from the internal BDIV_CLKIN clock, which can be selected from either ADC_CLK or ADC_MOD_CLK. You can control the BCLK  divider to setup the output bit clock. Typically, for TDM applications, the maximum BCLK recommended is 256.

    Correct, but please consider that the maximum offset supported by the channels of the  'ADC3101 is 255. The conditions you mention effectively will lead into an extra bit of offset between channels, just consider that a double offset will be seen in the data frame as each 33-bit channel already includes a 1-bit offset.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer