PGA2310: How tight are the switching timing characteristics for the SPI?

Hi Benjamin,

The timing specs given are minimum setup and hold times (or maximum delays before an output on the PGA transitions). It's not an issue to wait longer than those minimum times. For example, the 60ns max spec on SCLK Falling to SDO data valid specifies that after the SPI master pulls the SCLK line low, the PGA2310 will have valid data on its SDO line no more than 60ns later. If you attempted to read data before that 60ns window, it may not be valid yet. Waiting far longer doesn't make the data invalid, it just slows down your data rate.

Your optocouplers will add some uncertainty into the timing for setup and hold specifications, and may require you to slow down the SPI bus somewhat.

As an example, let's take the t_sds spec (SDI setup time): the PGA requires valid data to be present at its input 20ns before the SCLK rising edge. If you have a 4µs delay in your optocoupler for the SDI line, and 0µs on the clock optocoupler (as an extreme example), you'd need to add that 4µs delay to the setup time requirement, meaning you'd have to set up data 4.02µs before you toggle your clock high. In order to ensure that, you might choose a slower clock rate - say 100kHz or less - to ensure that you stay within the timing spec.

If your communication happens too fast, you may end up with invalid data in the PGA register, so if volume control isn't behaving predictably, you may need to decrease the clock rate some more to compensate.

Hi Benjamin,
I suspect that if you're using an SPI peripheral in a microcontroller, it can be configured update its output pin on the clock's falling edge. As long as you're running the clock slow enough, there should be plenty of time for the optoisolators to propagate that value before the clock rising edge.