Other Parts Discussed in Thread: PCM5122
Hi,
A customer asks for PCM5121 software mode register settings of I2S 3-Wire to us. The clock frequency he uses is BCLK=3.072 MHz and LRCK=48 kHz.
I showed an example settings as below, but he says PCM5121 did not output sound.
# Select Page 0
w 98 00 00
# Set the device into Powerdown
w 98 02 11
# Reset Device
w 98 01 11
# Select Page 0
w 98 00 00
# Set the device into Standby
w 98 02 10
# Page 44
#w 98 00 2c
# Select Page 0
w 98 00 00
# 8x/4x/2x FIR interpolation filter with de-emphasis
#w 98 2b 01
# Select Page 44
#w 98 00 2c
# Select Page 0
#w 98 00 00
# Wake from Standby
w 98 02 00
# Mute
w 98 03 11
# Exit standby
w 98 02 00
# Disable PLL
w 98 04 00
# The PLL reference clock is BCK
w 98 0d 10
# DAC clock source is PLL clock
w 98 0e 10
# P=1
w 98 14 00
# J=16
w 98 15 10
# D=0000
#w 98 16 00
#w 98 17 00
# R=2
w 98 18 01
# NMAC=2
w 98 1b 01
# NDAC=16
w 98 1c 0f
# NCP=4
w 98 1d 03
# DOSR=8
w 98 1e 07
# Ignore SCK and SCK halt detection, Disable clock auto set
w 98 25 1a
# Enable PLL
w 98 04 01
# I2S slave mode
#w 98 09 00
# 8x interpolation, Single speed
#w 98 22 00
# IDAC = 1024
w 98 23 04
w 98 24 00
# 24 bits, I2S
w 98 28 02
# offset = 0 BCK (no offset)
#w 98 29 00
# L-ch path <- Lch data, R-ch path <- R-ch data
#w 98 2a 11
# The volume for Left and right channels are independent
#w 98 3c 00
# Left Digital Volume: 0.0 dB
#w 98 3d 30
# Right Digital Volume: 0.0 dB
#w 98 3e 30
# Unmute
w 98 03 00
I can't check whether my example is correct, because we don't have the EVM. Please check my example and advise to us.
Best regards,
Akio Ito
