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AIC3204 with 96 KHz and 192 KHz sampling rates

Christos Nikolaou12204
Expert 1790 points

Hi,

 

I have a succesful project with a AIC32x4 running in 48 KHz sampling rate.

Now I need to proceed by adding the 96 KHz and 192 KHz sampling rates to the codec.

Is there any example that I can re-use for that? I tried to change the AOSR/DOSR/NDAC/NADC/MDAC/MADC but after quite some tries I couldnt make it work.

 

Below is the configuration sequence that is used right now for 48KHz sampling rate, can someone please point what changes are needed there for 96 KHz and 192 KHz?

 

;*****************************************************************
; Configure AIC32x4
;*****************************************************************
;Point to page 0                                        00, 0x00
;Reset codec                                            01, 0x01
;Point to page 1                                        00, 0x01
;Disable crude AVDD generation from DVDD                01, 0x08
;Enable Analog Blocks and LDO                           02, 0x01
;*****************************************************************
;* PLL and Clocks config and Power Up                          
;*****************************************************************
;Point to page 0                                        00, 0x00
;BCLK and WCLK is set as op to AIC3254(Master)          27, 0x0D
;PLL setting: PLLCLK <- MCLK and CODEC_CLKIN <-PLL CLK  04, 0x03
;PLL setting: J=8                                       06, 0x08
;PLL setting: HI_BYTE(D) for D=0x0780 (or 1920 decimal) 07, 0x07
;PLL setting: LO_BYTE(D) for D=0x0780                   08, 0x80
;For 32 bit clocks per frame in Master mode ONLY
;BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs        30, 0x88      
;PLL setting: Power up PLL, P=1 and R=1                 05, 0x91
;Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080         13, 0x00
;Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080         14, 0x80
;AOSR for AOSR = 128 decimal for decimation filters 1/6 20, 0x80
;Power up NDAC and set NDAC value to 8                  11, 0x88
;Power up MDAC and set MDAC value to 2                  12, 0x82
;Power up NADC and set NADC value to 8                  18, 0x88
;Power up MADC and set MADC value to 2                  19, 0x82
;*****************************************************************
;* DAC ROUTING and Power Up                                    
;*****************************************************************
;Select page 1                                          00, 0x01
;LDAC AFIR routed to HPL                                12, 0x08
;RDAC AFIR routed to HPR                                13, 0x08
;Select page 0                                          00, 0x00
;Left vol=right vol                                     64, 0x02
;Left DAC gain to 0dB VOL; Right tracks Left            65, 0x00
;Power up left,right data paths and set channel         63, 0xd4
;Select page 1                                          00, 0x01
;Unmute HPL , 0dB gain                                  16, 0x00
;Unmute HPR , 0dB gain                                  17, 0x00
;Power up HPL,HPR                                       09, 0x30
;Select page 0                                          00, 0x00
;*****************************************************************
;* ADC ROUTING and Power Up                                    
;*****************************************************************
;Select page 1                                          00, 0x01
;STEREO 1 Jack
;IN2_L to LADC_P through 40 kohm                        52, 0x30
;IN2_R to RADC_P through 40 kohmm                       55, 0x30
;CM_1 (common mode) to LADC_M through 40 kohm           54, 0x03
;CM_1 (common mode) to RADC_M through 40 kohm           57, 0xc0
;MIC_PGA_L unmute                                       59, 0x00
;MIC_PGA_R unmute                                       60, 0x00
;Select page 0                                          00, 0x00
;Powerup Left and Right ADC                             81, 0xc0
;Unmute Left and Right ADC                              82, 0x00
;*****************************************************************

 

Christos

 

  • 0
    TI__Mastermind 46195 points

    Christos,

    See Table 1 of http://focus.ti.com/lit/an/slaa404c/slaa404c.pdf. Basically, DOSR/AOSR should be 32 for 192ksps. Note that the correct prcoessing block for that filter should be chosen and that RC*32 >= MDAC*DOSR or MADC*AOSR. This is all mentioned in the table.

    Regards,

    J-

  • 0 in reply to J-
    Expert 1790 points

    Hi J,

     

    Thanks for answering.

    I've seen such posts that mention this, also I've tried to implement the AOSR/DOSR/etc dividers, yet it seems that it is not working.

    One thing though that it is not right now in the succesful example that I have (and in other examples eg from SLOS602A) is the absence of a 'working' example for setting properly the processing blocks. Although the guide you mention has such code snippets, it has not a complete working example for either 96 or 192 KHz sampling rates.

    Is there in any place a complete working example that has any sampling rate larger than 48 KHz that I can review?

     

    Regards,

    Christos

  • 0 in reply to Christos Nikolaou12204
    TI__Mastermind 46195 points

    Christos,

    See attached script file. Make sure that all other settings apply for your system (e.g. master clock frequency, supplies, etc.)

    Fullscreen 8877.AIC32x4_192000_KHZ.txt Download 
    ###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.288 MHz,
# BLCK = xxxxx MHz, WCLK = 192 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 32
w 30 0D 00 20
#
# NADC = 2, MADC = 8, dividers powered on
w 30 12 82 88
#
# AOSR = 32
w 30 14 20
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P17 and PRB_R13 selected
w 30 3C 11 0d
#
###############################################



###############################################
# Configure ADC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# Route IN1L to LEFT_P with 20K input impedance
w 30 34 80
#
# Route CM1L to LEFT_M with 20K input impedance
w 30 36 80
#
# Route IN1R to RIGHT_P with 20K input impedance
w 30 37 80
#
# Route CM1R to RIGHT_M with 20K input impedance
w 30 39 80
#
# Unmute Left MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3b 0c
#
# Unmute Right MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3c 0c
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################



###############################################
# Configure DAC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop: 5 time constants, 6k resistance
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Power up HPL/HPR
w 30 09 30
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

    Regards,

    J-

  • 0 in reply to J-
    Expert 1790 points

    Thanks J,

    That is what I was asking.

    Regards,

    Christos

     

  • 0 in reply to Christos Nikolaou12204
    Expert 1790 points

    Hi J,

     

    With the help of your example I think that I've managed to have these modes working ok in my setup (eZDSP5515)

    1. 48K/16bit   PRB_P1/PRB_R1/PTM_P4/PTM_R4

    2. 48K/32bit   PRB_P1/PRB_R1/PTM_P4/PTM_R4

    3. 96K/32bit   PRB_P7/PRB_R7/PTM_P4/PTM_R4

    4. 192K/32bit   PRB_P17/PRB_R13/PTM_P4/PTM_R4

     

    I notice though a clear difference in volume when I change to (4) whereas all the others (1),(2),(3) have the same volume/sensitivity. Is there something in PRB_P17/PRB_R13 that could explain that or am I missing something and all should have the same volume/sensitivity behaviour?

    All the above have common AIC setup (volume, routing etc) and only clock and PRB settings differ.

    Thanks,

    Christos

     

     

    P.S. Edit

    Actually I noticed that change even when I experimented having 48KHz/32bit and applying Filter C (PRB_P17/PRB_R13) in 48KHz mode instead of  Filter A (PRB_P1/PRB_R1).

  • 0 in reply to Christos Nikolaou12204
    TI__Mastermind 46195 points

    Hi Christos,

    On the ADC side, there will be a gain difference if the incorrect AOSR setting is selected. So using Filter C with AOSR=128 will yield a gain error. However, using AOSR = 32 for 192ksps should yield the same gain pass band gain as using AOSR = 128 for 48ksps, as shown in the filter graphs in the datasheet. Please verify AOSR setting as well as MADC*AOSR >= RC*32 setting for 192ksps.

    Regards,

    J-

  • 0 in reply to J-
    Expert 1790 points

    Hi J,

     

    Thanks for pointing out this constraint, it was the one that created the problem in 192KHz.

    I overlooked the RC constraints and used the PLL settings for 12MHz MCLK as they are indicated in table 5-25 of PLL configurations from the AIC3204 datasheet.

    With these, MADC=2 / NADC=7 / MDAC=7 / NDAC=2 and the P=1 / R=1 / J=7 / D=1680 , all constrain equations for the aforementioned modes (1),(2),(3) were ok apart from the MADCxAOSR/32>=RC specifically in (4) in 192KHz.

    So the ADC in 192KHZ/32bit was the one having the problem.

    I needed to change  J/D and MDAC/NDAC/MADC/NADC thus utilizing a new PLL/Clocking scheme in order to suit all.

     

    Now every mode is having the same level/gain and all working ok.

     

    Thanks again.

    Regards,

    Christos

     

  • 0 in reply to Christos Nikolaou12204
    TI__Mastermind 46195 points

    Hi Christos,

    I'm glad to hear that you got it working!

    Regards,

    J-