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TLV320AIC3206: MCLK requirements: slew rate, duty cycle

Dan Andersen
Genius 11460 points
Part Number: TLV320AIC3206

Are there any requirements on the MCLK used on our AIC3206 audio codec aside from 25MHz or 50MHz max depending on VDD level?  Any concerns with slew rate or duty cycle?  This seems fairly well defined for WCLK, BCLK, and data, but I can't find anything describing this for MCLK....

Thanks,

Dan

  • 0
    TI__Guru 57800 points

    Hi, Dan,

    There is no special timing requirement for MCLK clock apart from the maximum frequency described. In general, duty cycle should be kept around 45-55% of the clock period, as long as the minimum high or low cycle is above 50% of the maximum supported frequency. There is no specific rise and fall time spec, but  both should be kept below 10% of the period.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer