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PCM1864: Proper Master/Slave mode of Operation

Tim Simerly
Genius 9975 points
Part Number: PCM1864

Dear Support:

I am using the PCM1864 and wanting to use this device in master mode.  From the datasheet, there is a register at page 0, Register 32, that has bit5 value of MST_SCK_SRC of 0 for SCK or XI and 1 for BCK.  But in master mode, BCLK is an output.  So with this bit set makes no sense since there would be no reference clock feeding the PLL since the input is the resulting output.  Can you tell me a more clearer meaning (relative to what is in the datasheet) of this bit5 in master mode and exactly what it does?

Thanks,
Tim

  • 0
    TI__Guru 57800 points

    Hi, Tim,

    The issue you are pointing out is a typo on the old version of the datasheet, when bit 5 of Page 0: register 32 is set to 1, the selected clock for the system in Master mode is the PLL output.

    This typo has been fixed on the new version of the PCM1864 datasheet:

    http://www.ti.com/lit/ds/symlink/pcm1864.pdf 

    Regards,

    -Diego Meléndez López
    Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Genius 9975 points
    Hey Diego:

    Well that was helpful - thanks for making that clear. However I am still confused as to what all the bits in this register should be for master vs slave mode. Most confusing to me is the meaning and purpose of the LSB of this register, namely CLKDET_EN. In general, does CLKDET_EN need to be 0 for master mode and 1 for slave mode? That's what I am finding needs to be the case, but I don't understand why - can you explain when this bit should be set vs cleared and what all does it do? The datasheet is not very clear on what all this bit does. Please advise.

    Thanks,
    Tim
  • 0 in reply to Tim Simerly
    TI__Genius 9975 points
    Hey Diego:

    One other issue, I am using the LMB:

    www.ti.com/.../tida-01470

    and am finding that in order to get this to work in slave mode, I have to set this 0x20 register to 0x41. So the CLKDET_EN bit is set which hopefully your answer to my previous question will explain why this bit needs to be set. However having to set bit6 in this register is perplexing to me since there is nothing coming in on the SCK pin and I am using the external crystal. So I would have figured this register value should be 0x81 or 0x01, but not 0x41. Can you tell me why I need to set it to 0x41 when the SCK is inactive and at ground?

    Thanks,
    Tim
  • 0 in reply to Tim Simerly
    TI__Guru 57800 points

    Hi, Tim,

    The CLKDET_EN bit enables or disables the automatic clock detection (ACD) feature of the device. This feature allows the part to check the incoming clocks and based on the frequency of the reference clock (which is selected by bit 5 of the register in question), the device automatically configures the PLL and dividers to generate the required internal system clocks. If this feature is disabled, user should manually configure the PLL and dividers to generate the required system clocks.

    For Slave mode, the ACD feature can be either enabled or disabled, but we recommend to keep it enabled so user should not worry about the system clock configuration.

    For Master mode, the ACD feature will work only when the incoming master clock (which can be selected by bit 5 of register 0x20) has a frequency of  256×, 384×, or 512× multiple of the sampling rate, but as with slave mode case, user can manually configure PLL and dividers if required by disabling ACD. When the input clock does not meet the previously mentioned requirement, the automatic clock detection feature should be disabled and the user will need to configure manually the PLL and dividers.

    The reason the device is working in slave mode even if SCK is not provided is because when automatic clock detection feature is enabled, the device can take BCK as the input for the system clock and automatically set the PLL and dividers for the internal clocks when SCK is not present.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Genius 9975 points

    Hey Diego:

    Well that was not intuitively obvious.  :-)  Thanks for making that clear - sure didn't extract that from the datasheet, but makes sense now. 

    So that I am clear and hopefully better understand, should one want to set the ADC, DSP1 and DSP2 clock, and is using a crystal like 24.567 MHz, as was done with the LMB, and wants to set these clocks manually, can you advise how you figure out what the clock settings should be for master and slave modes vs letting the chip figure it out by setting CLKDET_EN?

    Thanks,
    Tim

  • 0 in reply to Tim Simerly
    TI__Guru 57800 points

    Hi, Tim,

    Basically, if the user would like to configure manually the coefficients for either master or slave mode, a couple conditions should be met:

    • ADC clock should be 128×Fs
    • DSP1 clock should be 256×Fs
    • DSP2 clock should be 512×Fs
    • BCLK should be either 32×Fs, 48×Fs, 64Fs or 256×Fs

    The LMB has a master clock with a typical audio frequency, so it will not be necessary to setup the PLL for sampling rates below 48KHz (as the DSP2 clock condition dictates). For Slave mode, you need to configure only the ADC, DSP1 and DSP2 dividers, while for master mode, the BCLK and LRCK dividers should be set.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Genius 9975 points

    Hey Diego:

    Well that was concise, clear and helpful - thanks.  I think I'll take the simpler path and use CLKDET_EN and slave mode.  :-)

    Thanks,
    Tim