CCS/TLV320AIC3206: AIC3206 codec AGC configuration

Diego,

Thanks for your time, I'll try the agc default settings, but what do you mean it should be done in the end-system.?

1) I tried the following agc settings and i kinda hear lot of airplane takeoff sound (air sound) in the background, probably amplified adc or dac noise i don't know

AIC3206_write( 86, 0xC2 ); // L-AGC configuration
AIC3206_write( 94, 0xC2 ); // R-AGC configuration

also tried just 80 for both AGCs meaning just enabled the agc and rest values are 0s

2) I apologize the registers I sent you were suggested by some c5545 dsp engineer to set the dac to 8000hz. here are the adc and dac resgister values i'm using. 8000 is required sampling rate. could you provide the right settings for high power high performance of adc and dac. I'm assuming the air noise in background is due to these setting issues.

AIC3206_write( 13, 0x02 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3206_write( 14, 0x00 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3206_write( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3206_write( 11, 0x87 ); // Power up NDAC and set NDAC value to 7
AIC3206_write( 12, 0x83 ); // Power up MDAC and set MDAC value to 12
AIC3206_write( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3206_write( 19, 0x8C ); // Power up MADC and set MADC value to 12

3) following are the register settings for IN1 to PGA routing, and I want all other inputs to be not routed or off.

AIC3206_write( 0, 0x01 ); // Select page 1
AIC3206_write( 52, 0x40 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3206_write( 55, 0x40 ); // IN2_R to RADC_P through 40 kohmm
AIC3206_write( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3206_write( 57, 0x03 ); // CM_1 (common mode) to RADC_M through 40 kohm

4) what about HPL,HPR(headphone amplifier ) settings for high performance?

Hi diego,

can you please reply to the above post. Thanks

hi, diego

wondering if you have a solution for my issues mentioned above?

V Pot,

 

End-system is a term refers to the system developed by the user where the device is being used. I meant that the AGC should be fine tuned in the final board with the final conditions like type of mic, enclosure, etc.

1-Do you notice a difference by disabling the AGC?. I would not expect the AGC to cause a high noise with the default settings. Maybe the noise is coming from a different source.

2-What are the input clock frequencies used? I need them to check if the dividers are set correctly. Actually, can you please share the full register settings used to configure the clocks? from the divider settings, I assume the PLL is being used.

3-The settings are fine, the rest of the inputs are not connected to the PGA.

4-There is no special requirement for the headphone amplifier setting on high-performance mode. Basically, high performance playback at 8KHz sampling rate  is achieved after configuring the codec to have a full-chip common mode of 0.9V, selecting power tune mode 1 (PTM_P1), processing block 7 and setting a DOSR of 768.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

hi diego,

1) with agc the noise increased. even without agc there is noise. and this noise is heard without any input.

2) here are the full codec settings
/* Configure AIC3206 */
AIC3206_write( 0, 0x00 ); // Select page 0
AIC3206_write( 1, 0x01 ); // Reset codec
C55x_delay_msec(1); // Wait 1ms after reset
AIC3206_write( 0, 0x01 ); // Select page 1
AIC3206_write( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3206_write( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3206_write( 123,0x05 ); // Force reference to power up in 40ms
C55x_delay_msec(40); // Wait at least 40ms
AIC3206_write( 0, 0x00 ); // Select page 0

/* PLL and Clocks config and Power Up */
AIC3206_write( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3206(Master)
AIC3206_write( 28, 0x00 ); // Data ofset = 0
AIC3206_write( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3206_write( 6, 0x07 ); // PLL setting: J=7
AIC3206_write( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3206_write( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3206_write( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3206_write( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
C55x_delay_msec(1); // Wait for PLL to come up
AIC3206_write( 13, 0x02 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3206_write( 14, 0x00 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3206_write( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3206_write( 11, 0x87 ); // Power up NDAC and set NDAC value to 7
AIC3206_write( 12, 0x83 ); // Power up MDAC and set MDAC value to 12
AIC3206_write( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3206_write( 19, 0x8C ); // Power up MADC and set MADC value to 12


/* DAC ROUTING and Power Up */
AIC3206_write( 0, 0x01 ); // Select page 1
AIC3206_write( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3206_write( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3206_write( 0, 0x00 ); // Select page 0
AIC3206_write( 64, 0x02 ); // Left vol=right vol
AIC3206_write( 65, 0x20 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3206_write( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3206_write( 0, 0x01 ); // Select page 1
AIC3206_write( 16, 0x05 ); // Unmute HPL , 0dB gain
AIC3206_write( 17, 0x05 ); // Unmute HPR , 0dB gain
AIC3206_write( 9 , 0x30 ); // Power up HPL,HPR
C55x_delay_msec(1 ); // Wait 1 msec

/* ADC ROUTING and Power Up */
AIC3206_write( 0, 0x01 ); // Select page 1
AIC3206_write( 52, 0x40 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3206_write( 55, 0x40 ); // IN2_R to RADC_P through 40 kohmm
AIC3206_write( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3206_write( 57, 0x03 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3206_write( 59, 0x00 ); // MIC_PGA_L unmute
AIC3206_write( 60, 0x00 ); // MIC_PGA_R unmute
AIC3206_write( 51, 0x00 ); // SetMICBIAS

AIC3206_write( 0, 0x00 ); // Select page 0
AIC3206_write( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3206_write( 82, 0x00 ); // Unmute Left and Right ADc
AIC3206_write( 83, 0x00 ); // Unmute Left and Right ADC
AIC3206_write( 84, 0x00 ); // Unmute Left and Right ADC
AIC3206_write( 86, 0x80 ); // L-AGC configuration
AIC3206_write( 94, 0x80 ); // R-AGC configuration

Hi diego,

any thoughts on the above config settings?. Thanks in advance.

Hi, V Pot,

Thanks for the feedback. I took a look to the register settings and have a couple comments:

• I assume the input clock is 12MHz, if so, the PLL coefficients are correct.
• The divider settings seems different from the comments , however, the result should be the same. Why did you changed DOSR from 128 to 512?.
• Please note that the gain used is quite high and any noise on the DAC will be increased.
• On the ADC side, the register settings seems correct, there is no obvious issue which can be causing noise.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

diego,

1)don't follow the comments they are not right.
2) I changed the DOSR to 512 based on suggestion by your ti support, to make the DAC at 8000 sample rate and also to satisfy the requirement in 2.4.6 of article www.ti.com/.../slaa463b.pdf
3) can you provide the right settings for high power and high performance output, with 8000 sampling rate both adc and dac. also show satisfy the requirements shown in 2.4.6

V Pot,

Thanks for the feedback.

I am attaching an example script for the high performance playback and recording with sampling rate of 8KHz.

Playback-Recording(8KHz).cfg

Regards,

-Diego Meléndez López
Audio Applications Engineer