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TAS2560: How Can We Define TAS2560's MCLK BCLK LRCK Clock Rates in PPC3

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: TAS2560

Hi Sirs,

Would you pls advise how can we can configure the TAS2560's MCLK, BCLK and LRCK rates in PPC3 since there is no system integration page as other Smart Amp devices?

Thank you and Best regards,

Wayne Chen
05/09/2018 

  • 0
    TI__Mastermind 20085 points
    Hi Wayne,

    The person in charge is out of the office. He will be responding with further information tomorrow.

    Best Regards
    José Luis Figueroa
    Audio Applications Engineer
  • 0 in reply to José Luis
    TI__Genius 15950 points

    Hi Luis,

    Would you pls assist us to manage startup code (and how to configure them) for:

    MCLK = 24.576MHz 
    BCLK= 512kHz
    LRCK= 16kHz

    Thank you and Best regards,

    Wayne Chen
    05/11/2018

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Genius 15950 points
    Hi Luis,

    Would you pleas assist us to check the TAS2560 clock configuration:

    1. BCLK ratio
    ASI_BDIV Register( register 0x1A)=0xA0 -> BCLK ratio = 32
    Since BLCK = BCLK_ratio * sample rate -> BCLK_ration = 16 (bit) * 2 (channel) = 32

    2. PLL clock input
    TAS2560_PLL_CLKIN register(register 0x0F)=0x01, select PLL clock's input=BCLK (reference to Linux driver)

    3. PLL clock

    In order to fulfill the requirement of PLL clock = 32 * BCLK
    Following TAS2560 datasheet: PLL clock = 1024 * sample rate

    PLL clock was generated from BCLK, PLL clock= 32 * BCLK

    PLL clock = 32 * BCLK
    PLL clock = (BCLK * J.D)/P
    P= 1 (register 0x0F)
    J= 32 (register 0x10)
    D= 0 (register 0x11 + register 0x12)

    Would you pls assist us to check if there is missing or mistake?

    Thank you and Best regards,

    Wayne Chen
    05/14/2018
  • 0 in reply to Wayne Chen (Audio AE)
    TI__Guru** 109825 points
    Hi Wayne,

    The clock configurations seem to be correct. By the way, our team is currently working on the End System Integration for TAS2560. This was not initially included since the TAS2560 was mainly purposed to work as a stereo pair along with other TAS255x device. I'll let you know as we have more information about this.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • 0 in reply to Ivan Salazar
    TI__Genius 15950 points

    Hi Ivan,

    Thanks for your concern. We are supporting the TAS2560 as a standalone mono CLass-D amplifier. We tried to configure the TAS2560 with our calculation, but it was in vein. Our PPC3's default configuration (ROM mode1 and ROM mode 2) are compatible with 12.288MHz MCLK, 3.072 MHz BCLK and 48kHz LRCK only.

    Here we need product line's help:

    1. Add System Integration page to the TAS2560 device to dump CFG with customer's defined clock rate.
    2. Would you pls assist us to modify the enclosed CFG to fit 24.576MHz MCLK, 512kHz BCLK and 16kHz LRCK before official PPC3 tool?
    3. We found Page 0x32 instructions from PPC3's I2C log when setting the Vpeak voltages, however, the page 0x32 seems hidden registers in the datasheet. Do we have software guidance to configure Vpeak and speaker impedance?  
    4. Need an instruction (or interface) to setup high efficiency and normal efficiency modes. 

    Thank you and Best regards,

    Wayne Chen
    05/15/2018

    TAS2560_4.2V_2W_4ohm_48kHz_64FS_0x98.cfg
    TAS2560_5.8V_4W_4ohm_48kHz_64FS_0x98.cfg

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Guru** 109825 points
    This will be handled offline through e-mail.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators